JPS58155731A - Defect inspecting device - Google Patents

Abstract

PURPOSE:To enable to detect various defects in a high degree of optical accuracy by a method wherein an analogical-addition is performed by making a combination in such a manner that one half of the output signals of a plurality of detectors is formed in positive code and the remaining half is formed in negative code. CONSTITUTION:A plurality of detectors are provided for every region of a plurality of vacant spaces on an IC pattern. The output signals sent from these detectors are designated as e1-e8. Or these signals e1-e8, optional two of them are paired and the sum or the difference of the pair can be formed as the first stage 21-11-21-14. Then, two of the output signals of the first stage are paired and the sum or the difference can be formed as the second stage 21-21-21-22. The sum or the difference can be formed between the output signals of the second stage as the third stage 21-31. Thus, a defect detecting signal e0 is composed of. Through these procedures, the various defects, generated on the IC whereon a patterning is performed, or a large scale IC pattern chip, or a pellet, can be detected at a high degree of optical accuracy in a non-contacted and non- compared state.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit pattern defect inspection device that optically and non-contact detects defects occurring in patterned semiconductor integrated circuit chips.

In particular, the aim is to improve defect detection accuracy.

Many optical defect inspection devices have already been proposed for detecting circuit pattern defects in photomasks used in the formation of integrated circuits or large-scale integrated circuits (hereinafter referred to as integrated circuits) on substrates such as silicon wafers, and some of them have not yet been put into practical use. It is provided. However, no equipment has yet appeared that uses a photomask on a silicon wafer to (automatically) inspect chips or pellets (hereinafter referred to as integrated circuit chips) on which integrated circuits are formed for defects (including foreign matter such as adhering dust). I haven't.

Therefore, even today, visual inspection using an optical microscope is still used to inspect integrated circuit chips. In this inspection method, the efficiency of inspection.

It is said that there are problems with the number of inspectors and the reliability of test results, and there is a strong desire for improvements in testing methods.

As a way to deal with this current situation of visual inspection,
Efforts have been made to facilitate the detection of pattern defects and improve work efficiency (see Japanese Patent Laid-Open No. 54-2543). Even with this improved visual inspection method,
Also, no matter how skilled.

There is room for personal error to enter the test results, and problems remain with the reliability of the test.

By the way, since there is an automatic photomask defect inspection device, could it be used for defect inspection of integrated circuit chips? Everyone will probably notice this. Many proposals have already been made. A certain Ll (yo.

If an integrated circuit chip is set at a predetermined position in a commercially available optical inspection apparatus for photomasks and an attempt is made to inspect it, it is clear that all such attempts will fail. This is because the optical system of these optical inspection devices for photomasks assumes that the photomask to be inspected is a transparent sample in the visible light region, and the transmission type optical system is assembled. It is in. An integrated circuit chip using silicon Ueno as a substrate does not transmit light in the visible light range.
Therefore, when an integrated circuit chip having a silicon substrate as a substrate is to be inspected, the defect detection optical system must be of a reflective type, and the defect detection optical system uses light in the visible wavelength region as an inspection means.

So, wouldn't it be a good idea to simply replace the transmissive optical system of the photomask defect inspection system with a reflective optical system? An idea will be born.

However, if we examine through thought experiments the configurations of all of these inspection devices that have been proposed or put into practical use, we will see that when a transparent sample changes to a reflective sample, The possible configurations are not mirror images of the configurations possible for reflective samples. Therefore, this simple conversion operation does not hold true. The method based on this idea cannot achieve the purpose of defect inspection of the target sample.

As a result of the above studies, we found that [1]
It has been found that in order to achieve O"i, given the reflective nature of this sample, unique defect detectable methods and configurations must be developed.

In response to the current situation, methods for inspecting some integrated circuit chips for foreign matter have been proposed. The first method is to irradiate a point on the sample surface with a polarized laser and detect this point with a microscope equipped with a polarizing plate, thereby detecting only the foreign matter without detecting the circuit pattern on the sample surface -L. To detect. That is what it is. The second method is a development of this method, in which S-polarized laser beams are irradiated from four directions around nine areas, and two pairs of lasers in orthogonal directions use 1.-sa of different wavelengths.

The detection system performs wavelength separation and a detector is placed for each wavelength to detect only foreign matter without detecting the circuit pattern on the sample surface. That is what it is.

These methods are revolutionary in that they can detect foreign material defects on integrated circuit chips. But...

It is insufficient in that the only detectable defect is foreign matter.

In order to solve the above-mentioned problems with the prior art, the inventors of the present application first attempted to optically and non-contact detect foreign particles, disconnections, and other various defects on integrated circuit chips. We proposed a defect inspection device that made it possible to
No. 96920). An object of the present invention is to provide a plurality of detectors in each area of the previously proposed defect inspection apparatus.

It is an object of the present invention to provide a defect inspection device equipped with a signal synthesizing means that can further improve detection accuracy.

The characteristics of the present invention are as follows.

Multiple detectors are provided for each of multiple spatial regions, and one defect detection signal is output by adding half of these detector output signals with a positive sign and the other half with a negative sign. The object of the present invention is to adopt a configuration in which signal combining means is provided.

The present invention will be explained below with reference to one drawing.

FIG. 1 shows the signal synthesis circuit shown in the introduction (FIG. 6). In Fig. 1, 10-1 to 10-8 are detectors arranged corresponding to areas A-H shown in Fig. 3, and 11-1 to 11-8 are connected to each detector. This is a preamplifier with a built-in design. Also, 14-1 to 14-8
and 15 are resistors, and 16 is an operational amplifier,
This operational amplifier adds the output signals of the preamplifiers 11-1 to 11-8. This configuration corresponds to the case where one detector is provided in each of the regions A to H shown above.

However, as mentioned in the introduction, by providing a plurality of detectors for each region, it is possible to prevent detection failure due to the size of defects. The present application attempts to obtain a single defect detection signal with a high detection separation by combining the output signals of these multiple detectors when each area has a plurality of detectors.

To simplify the explanation, the number of detectors for each region is assumed to be two, and among the eight regions A to H, A,
Consider the case where detectors are placed in four areas C, E, and G.

Figure 2 shows Z' X(,I)O under this assumption.
This is an example of spatial arrangement within a plane, and Figure 3 shows areas A, C, E,
It shows a state in which a group of detection systems (consisting of a detector and a preamplifier) spatially arranged in G is projected onto a 9171 plane. In FIG. 2, 3 is a patterned chip; 6 is a patterned chip;
is an arrow indicating the direction of the irradiation beam. 8-11~8-
Reference numeral 22 denotes a single lens or a compound lens, which condenses reflected and diffracted light due to a defect.
8-21 etc. are arranged on the circular arc 12. 9-1.9-
2 is a slit. 10-1.10-2 ii detectors, each of which is connected to a preamplifier 11-1.11-2. The above corresponds to area A, and equivalent items are arranged in the other three areas C2E and G, respectively.

In FIG. 3, reference numeral 28 is an arrow line indicating the scanning direction of the light beam 6 on the wafer surface. Now, assuming that the scanning direction is the X-axis and the direction perpendicular thereto is the y-axis, the relative positional relationship of each detection system projected onto the wafer surface is as shown in FIG. That is, the direction of the detection system in area A is at a position of 225 degrees with respect to the X axis, and the detection systems in areas C and EG are at positions sequentially shifted by 90 degrees from this. These detectors are shown in FIG.

10-1.10-2. ..., 10-8. Although not shown in FIG. 3, each detector includes a preamplifier 11-1. ll-2,...,1
18 are connected.

The subject matter of this application is a signal synthesizing means that processes eight detector output signals and outputs them as one defect detection signal. FIG. 4 shows a circuit diagram including the detector. Reference numeral 21 denotes a signal synthesis circuit according to an embodiment employed in the present application. In the case shown in FIG. 1, since there was one detector for each region, simple addition was sufficient to extract the defect signal detected by any of the detectors. However, when a plurality of detectors are provided for each region.

Signal synthesis methods other than simple addition become possible.

An example is shown in FIG. eIt e2+・・・・・・
+e8 are the detectors 10-1, 10-2, respectively. ...
..., shows the output signal from 10-8. By pairing any two of these e1 to e8, the sum or difference of the pair can be created, and this is the first stage 21-]]~21-1
It is 4. Two of the output signals of the first stage can then be combined to form the sum or difference of the pair, which is the second stage's output signal.
Stage 2]-21 to 2]-22. Finally, a sum or difference can be made between the output signals of the second stage.

This is the third stage 21-31.

Now, the output signal from the detector + e, (1 = 1 to 8)
When creating a set of two from among , it is not just a matter of creating a set, but it must be suitable for a certain purpose.

Consider this below. FIG. 6 is a plan view of the chip 3, which is roughly divided into internal In and external O. The In part generally has a dense circuit pattern 7, and the 00 part generally has a sparse circuit pattern. Assume that a certain part of the surface of this chip is scanned and the output waveform of each detector is observed. The scanning location is denoted by t. Then, the observed detector output signal is.

For example, as shown in FIG. 7, e is the 00 part.

If it is the In part, it is scanned again to g, which is the 00 part. In the example in Figure 7, the DC is
The AC component and the AC component are superimposed. If there is a defect at point t, a defect signal appears at time 111 corresponding to 2 points)] in the output signal. This defect signal does not appear on all eight detectors. The detector where the defect signal appears is determined by the size, shape, and orientation of the defect. The defect may exist not only in the dense In part of the two-circuit pattern (but also in the sparse 00 part).
A defective signal will appear during this time period.

Assuming that the output waveform shown in Figure 7 appears, the defect at time 1h can be extracted by cutting this output waveform with a threshold that is slightly larger than the peak value of (DC component) + (AC component). . However, if there is a defect in the two time periods e or g, the extraction based on the threshold value will result in the extraction being omitted. On the other hand, if we decide the threshold value so that we can extract the defects that appear in the 2 time periods e or g, then the DC
Ingredients become a problem. Note that at this time, a method of providing a threshold value with a window of two time periods may also be considered. However, the levels of the DC and AC components vary depending on their location within a single chip. The occurrence situation differs between chips. Establishing a fixed level window for reasons such as this is ineffective.

Therefore, in this embodiment, 4 of the 8 detector output signals have a positive sign and the remaining 4 have a negative sign and are added in analog form to eliminate or reduce the DC component, thereby producing a single signal. The configuration is such that a defect detection signal is obtained. That is, in Figure 5,
The configuration is such that a difference is taken in at least one stage from the first stage to the third stage. Such combinations are shown in Table 1.

Nα1 in Table 1 is Nα2. Nα3. Nα4 is Nα5゜Nα when the sum is taken in one stage and the difference is taken in the remaining two stages.
6. Nα7 is a case where the quantity is calculated in one stage and the sum is calculated in the remaining two stages.

Here, with respect to the spatial arrangement of the detectors, "the same direction j and"
The term "perpendicular direction" is defined with reference to FIG. The same direction refers to the directions of regions that are symmetrical to each other with respect to the coordinate origin, such as regions A and E, C and G, etc. Further, the perpendicular direction refers to the direction of an area shifted by 90 degrees from the area of interest, such as A and C9, A and G, and E and C2.

Now, when the detector output signals e1 and C2 of region A are used as a starting point, and in the first stage of FIG. 5, a partner for making a difference or a sum is determined, detector output signals in the same direction or in the orthogonal direction are selected. In this way, if we prepare each other's opponents in Table 2, Table 3, 1st row, 2 and then decide on each other's opponents in the 2nd and 3rd rows, the combination is 1. For example, N in Table 1.
Table 2 corresponds to α3 (difference→sum→difference), and Table 3 corresponds to Nα6 (sum→difference→sum). Through all the combinations according to Table 1, four of the eight detector output signals e1 to e8 are added with positive signs and the remaining four are added with negative signs. Of course, combinations other than those shown in Table 1 are also possible in which eight signals are arbitrarily combined and four are added with positive signs and the remaining four with negative signs, but these do not eliminate or reduce the DC component. It is not suitable for the purpose of

As described above, the eight detector output signals in the two examples can be finally combined into one signal.

Moreover, it is obtained as a signal with DC components eliminated or reduced, which is convenient for extracting defect signals.

If the signal becomes like this, the circuit element 9 with a constant threshold value
For example, it is possible to generate a binary defect signal using a comparator.

Below, we have shown a case in which two detectors are spatially arranged in each of four regions perpendicular to each other.
There are also 2.6°8 available areas. In this way, the number of utilized areas is set to 2.6.8, and the number of detectors provided in each area is further increased to 3, 4, etc.
Even in the case of ・, it can be made into one defect detection signal by reducing or expanding the above-described embodiment.

As explained above, according to the present invention, half of the output signals of at least four or more (even number) detectors have a positive sign and the other half have a negative sign. Patterned integrated circuits or large-scale integrated circuit pattern chips, which have been difficult to detect in the past, by combining and adding analog signals to obtain a single defect detection signal.

or Pellet), the various defects that occur in -L,
Detection can be performed optically without contact and without comparison, with high detection accuracy.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the conventional configuration of signal synthesis, Figure 2 is a detector spatial arrangement diagram when two detectors are used in the same area,
Fig. 3 is a projection diagram of the detector position onto the wafer surface, Fig. 4 is an overall configuration diagram of signal synthesis, Fig. 5 is a signal synthesis circuit diagram of an embodiment of the present invention, and Fig. 6 is a diagram for explaining the scanning line position. The chip plan view, FIG. 7, is a diagram showing an example of a signal waveform based on constant scan lines. Explanation of symbols 3... Chip 8... Lens 9... Slit 10-1 to 10-8... Detector 1
1-1 to 11-8... Preamplifier 21... Signal synthesis circuit 21-11 to 21-14... First stage 2 of signal synthesis circuit
1-21.21-22...Second stage 21 of the signal synthesis circuit
-31 ・・・・・・・・・3rd stage representative patent attorney for signal synthesis circuit Junnosuke Nakamura 51-1 Figure 2 Figure 1-3 Figure 4 Figure 5

Claims (1)

[Claims] By scanning the surface of an integrated circuit pattern with coherent light having a predetermined optical spot diameter perpendicular to the surface, the reflected diffracted light is converted into a plurality of beams that the reflected diffracted light generated by a normal integrated circuit pattern would not normally reach. In the apparatus for detecting a defect in the integrated circuit pattern by detecting it with a light detection means provided in a spatial region of L.
Multiple detectors are provided for each region of the multiple spatial regions, and half of the output signals of each detector are added with a positive sign and the other half with a negative sign, and one defect detection signal is output by adding analog signals. A defect inspection device characterized by being provided with a synthesis means.