JPS58154944A - Signal matrix circuit - Google Patents
Signal matrix circuitInfo
- Publication number
- JPS58154944A JPS58154944A JP57037211A JP3721182A JPS58154944A JP S58154944 A JPS58154944 A JP S58154944A JP 57037211 A JP57037211 A JP 57037211A JP 3721182 A JP3721182 A JP 3721182A JP S58154944 A JPS58154944 A JP S58154944A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- signals
- input terminal
- turned
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H40/00—Arrangements specially adapted for receiving broadcast information
- H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
- H04H40/27—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
- H04H40/36—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/60—Receiver circuitry for the reception of television signals according to analogue transmission standards for the sound signals
- H04N5/607—Receiver circuitry for the reception of television signals according to analogue transmission standards for the sound signals for more than one sound signal, e.g. stereo, multilanguages
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Multimedia (AREA)
- Stereo-Broadcasting Methods (AREA)
- Television Receiver Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、両独方式の音声多重回路を有するテレビ受傷
機において、受信した音声多重信号から希望する音声信
号を得るための信号マド1ノクス回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal multiplex circuit for obtaining a desired audio signal from a received audio multiplex signal in a television receiver having a dual-German audio multiplex circuit.
従来の西独方式の信号マ) IJクス回路は、第1図(
&)、(b) K示す回路でめった。(a)は入力側に
L十Rの信号(L信号は左信号、R信号は右信号)と2
Rの信号を加えて、2Rの信号を増幅率が1/2の反転
増幅器1で増幅して直接出力信号R(−R:とすると共
に、加算器2に加えてL+R−Rによシ出力信号りを得
るものであり、また(b)は入力側に(L+R)/2と
Rの信号を加えて、Rの信号はその11出力信号とする
と共に、スイッチ3力;84RKある場合には(L+R
)/2を増幅率2倍の反転増幅器4で増幅して加算器5
でR信号を加え、−L−R+ Hにより出力信号L(−
L)を得るものである。The conventional West German system signal generator (IJ) circuit is shown in Figure 1 (
&), (b) K is rare in the circuit shown. (a) has L + R signals on the input side (L signal is the left signal, R signal is the right signal) and 2
Adding the R signal, the 2R signal is amplified by the inverting amplifier 1 with an amplification factor of 1/2, and the direct output signal R (-R:) is added to the adder 2. (b) adds the (L+R)/2 and R signals to the input side, the R signal is the 11 output signal, and the switch 3 output; if there is 84RK, (L+R
)/2 is amplified by an inverting amplifier 4 with an amplification factor of 2, and then sent to an adder 5.
Add the R signal at -L-R+H to output signal L(-
L).
しかし、上記の信号マ) IJり九回路は、1/2や2
倍の増幅率の反転増幅器が必要であった。However, the above signal ma) IJ Ri 9 circuit is 1/2 or 2
An inverting amplifier with twice the amplification factor was required.
本発明の目的は原理的に抵抗とスイッチおよび位相反転
部のみで構成することができ、1/2や2倍の増幅率の
反転増幅器を必要としない音声多重回路用の信号マ)
IJクス回路を提供することである。The object of the present invention is to provide a signal amplifier for an audio multiplex circuit which can be configured with only resistors, switches, and phase inverters in principle, and does not require an inverting amplifier with an amplification factor of 1/2 or 2.
The purpose of the present invention is to provide an IJ bus circuit.
以下、本発明の実施例について説明する。第2図はその
一実施例を示す図で、一方の入力端子6はメイン信号と
しての(L+R)/2の信号が加わる端子、他方の入力
端子7はサブ信号としてのRの信号が加わる端子であり
、各々の信号は直流カット用のコンデンサC1、あるい
はレベル調整用の可変抵抗VRと直流カット用のコンデ
ンサCIを経て、トランジスタQ+・Q!のペースに加
わっている。抵抗R1〜R3はトランジスタQ1のバイ
アス設定用、抵抗R4〜R,はトランジスタQ2のバイ
アス設定用である。トランジスタQ1はそのエミッタか
ら直流カット用コンデンサCs、 C4により出力信号
が取抄出され、トランジスタQ2はエミッタから直流カ
ット用コンデンサC1により、またコレクタから直流カ
ット用コンデンサC・により出力信号が取り出されてい
る。この場合、トランジスタQzの工ばツタには(L
十R) / 2の信号が現われ、トランジスタQ2のコ
レクタには−RO信号が現われ、同トランジスタQ宜の
エミッタにはRの信号が現われる。そして、トランジス
タQsの工電ツタに現われる信号(L+R)/2は一方
で抵抗R・〜R1(l を経てアナログスイッチ80入
力端子8畠に入力し、他方で抵抗R11・R12によプ
トランジスタQ1のコレクタに現われる信号−Rと混合
され抵抗RIs ” R14を経てアナログスイッチ8
0入力端子8b K入力する。またトランジスタQlの
エミッタに現われる信号Rは抵抗R11〜Rttを経て
アナログスイッチ8の入力端子8cに入力する。アナロ
グスイッチ8は4個のスイッチS1〜S4を内蔵し、こ
れらは3人力4出力のスイッチ制御回路9により制御さ
れるようKなっている。すなわち、スイッチ制御回路9
にモノラル選択信号X、サブ選択信号y1ステレオ選択
信号2を入力した場合、アナログスイッチ8の各スイッ
チS1〜S4は次表のように切換わる。但し、オンは「
1」で、オフは「0」で示した。Examples of the present invention will be described below. FIG. 2 is a diagram showing an example of this, where one input terminal 6 is a terminal to which a (L+R)/2 signal as a main signal is applied, and the other input terminal 7 is a terminal to which an R signal as a sub signal is applied. Each signal passes through a capacitor C1 for DC cut, or a variable resistor VR for level adjustment, and a capacitor CI for DC cut, and is then connected to transistors Q+, Q! is joining the pace of Resistors R1 to R3 are used to set the bias of the transistor Q1, and resistors R4 to R are used to set the bias of the transistor Q2. The output signal of the transistor Q1 is taken out from its emitter by the DC cut capacitor Cs, C4, and the output signal of the transistor Q2 is taken out from the emitter by the DC cut capacitor C1, and from the collector by the DC cut capacitor C. . In this case, (L
A signal of R)/2 appears, a -RO signal appears at the collector of the transistor Q2, and a signal R appears at the emitter of the transistor Q2. Then, the signal (L+R)/2 appearing at the power supply terminal of the transistor Qs is inputted to the input terminal 8 of the analog switch 80 via the resistor R. It is mixed with the signal -R appearing at the collector of the analog switch 8 through the resistor RI
0 input terminal 8b K input. Further, the signal R appearing at the emitter of the transistor Ql is input to the input terminal 8c of the analog switch 8 via the resistors R11 to Rtt. The analog switch 8 includes four switches S1 to S4, which are controlled by a switch control circuit 9 with three manpower and four outputs. That is, the switch control circuit 9
When the monaural selection signal X, the sub selection signal y1, and the stereo selection signal 2 are input to the input signal, the switches S1 to S4 of the analog switch 8 are switched as shown in the following table. However, on is “
1", and "0" indicates off.
8d−8hは出力端子であり、その出力端子ad〜8f
は抵抗R1@5R1−で成る出力回路に、また出力端
子8g 、ahは抵抗R,、R21で成る出力回路に接
続されている。8d-8h are output terminals, and the output terminals ad-8f
are connected to an output circuit made up of resistors R1@5R1-, and output terminals 8g and ah are connected to an output circuit made up of resistors R, , R21.
第3図は第2図に示した回路の等価回路であシ、これを
参照して動作を説明する。各抵抗は、R@/R,=2/
1、R11/ R11= 1 / 2、Rn/Rn=2
/1にその比率が設定されており、従ってアナログスイ
ッチ8の入力端子8aには(L+R)/2の信号を1/
3にした信号(L十R)/6が加わり、入力端子8b
Kは(L + R) / 2の信号を2/3にした信号
(L+R)/3と−Rの信号を1/3にし大信号−R/
3との合計のL/3の信号が加わ)、入力端子8c K
はRの信号を1/3にした信号R/3が加わる。FIG. 3 is an equivalent circuit of the circuit shown in FIG. 2, and the operation will be explained with reference to this. Each resistor is R@/R,=2/
1, R11/R11= 1/2, Rn/Rn=2
The ratio is set to 1/1, so the input terminal 8a of the analog switch 8 receives a signal of (L+R)/2.
3 signal (L + R)/6 is added, input terminal 8b
K is a signal (L + R) / 3 which is the signal of (L + R) / 2 reduced to 2/3 and a large signal -R / which is the signal of -R which is reduced to 1/3.
3), input terminal 8c K
A signal R/3, which is 1/3 of the R signal, is added.
モノラル選択の場合は、前述の表の↓うK、スイッチS
1 とSsがオン、S!と54がオフとなるので、入力
端子8aに加わる(L+R)/6の信号が両出力端子8
d・8hから出る。またサブ選択の場合は、スイッチS
1 と52がオフ、Ss とS4 がオンとなるので、
入力端子8Cに加わるR/3の信号が両出力端子8d・
8hから出る。更にステレオ選択の場合には、スイッチ
S1 とSsがオフ、S! と54がオンとなるので、
入力端子8bに加わるL/3の信号が出力端子ad K
出、入力端子8c K加わるR/3の信号が出力端子8
hK出る。For monaural selection, press ↓K and switch S in the table above.
1 and Ss are on, S! and 54 are turned off, the signal of (L+R)/6 applied to input terminal 8a is applied to both output terminals 8
Leave from d.8h. In addition, in the case of sub selection, switch S
1 and 52 are off and Ss and S4 are on, so
The R/3 signal applied to input terminal 8C is applied to both output terminals 8d.
Leaves at 8h. Furthermore, in the case of stereo selection, switches S1 and Ss are off, and S! and 54 is turned on, so
The L/3 signal applied to input terminal 8b is output terminal ad K
output, input terminal 8c R/3 signal added to output terminal 8
HK comes out.
なお、第2図に示す入力端子6.7に、逆極性の信号−
(L + R) / 2、−Rを加えた場合には、アナ
ログスイッチ8の出力端子8d、8hKは第3図に示し
た信号の逆極性の信号が出る。Note that a signal of opposite polarity -
When (L+R)/2, -R is added, the output terminals 8d and 8hK of the analog switch 8 output signals with the opposite polarity of the signals shown in FIG.
以上のように1本発明によれば、分割用の抵抗とスイッ
チおよび位相反転部によ・り極めて簡単K。As described above, according to the present invention, the dividing resistor, the switch, and the phase inverter are used, making it extremely simple.
西独方式の音声多重信号からステレオ、モノラル、サブ
の信号を得ることができるという特徴がある0It is characterized by being able to obtain stereo, monaural, and sub signals from West German audio multiplex signals.
第1図(II)・(1))は従来の信号マ) IJクス
回路の回路図、第2図は本発明の一実施例の信号マトリ
クス回路の回路図、第3図は第2図の等価回路の回路図
である。
6・T・・・入力端子、8・・・アナログスイッチ、9
・・・スイッチ制御回路。
L?(!¥り、暑(早)、(Fig. 1 (II) and (1)) is a circuit diagram of a conventional signal matrix circuit, Fig. 2 is a circuit diagram of a signal matrix circuit according to an embodiment of the present invention, and Fig. 3 is a circuit diagram of a conventional signal matrix circuit. It is a circuit diagram of an equivalent circuit. 6.T...Input terminal, 8...Analog switch, 9
...Switch control circuit. L? (!¥ri, heat (early), (
Claims (4)
号を1/3倍した第2信号と、上記メイン信号を2/3
した信号および上記サブ信号を一1/3倍した信号を合
計した第3信号とを得、モノラル選択時に上記第1信号
を左右の出力端子に1サブ選択時に上記第2信号を左右
の出力端子に各々出力させ、ステレオ選択時に上記第1
信号を左右の一方の出力端子に出力させると共に上記第
2信号を左右の他方の出力端子に出力させるように上記
第1乃至第3信号をスイッチ選択して成ることを%黴と
する信号マトリクス回路。(1) A first signal that is 1/3 times the main signal, a second signal that is 1/3 times the sub signal, and 2/3 the above main signal.
When monaural is selected, the first signal is sent to the left and right output terminals, and when 1 sub is selected, the second signal is sent to the left and right output terminals. respectively, and when stereo is selected, the first
A signal matrix circuit comprising a switch selection of the first to third signals so that the signal is output to one of the left and right output terminals, and the second signal is output to the other left and right output terminal. .
号がRであることを特徴とする特許請求の範囲第1項記
載の1d号マ) IJクス回路。(2) The IJ box circuit according to claim 1, wherein the main signal is (L+R)/2 and the sub signal is R.
うにしたことを特徴とする特許請求の範囲第1項記載の
信号マトリクス回路。(3) The signal matrix circuit according to claim 1, wherein the first to third signals are obtained by resistor division.
オ選択を、上記第1乃至第3信号が入力するアナログス
イッチの制御により行なうようにしたことを特徴とする
特許請求の範囲第1項記載の信号マトリクス回路。(4) The monaural selection, the sub-selection, and the stereo selection are performed by controlling an analog switch to which the first to third signals are input. signal matrix circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57037211A JPS58154944A (en) | 1982-03-11 | 1982-03-11 | Signal matrix circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57037211A JPS58154944A (en) | 1982-03-11 | 1982-03-11 | Signal matrix circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58154944A true JPS58154944A (en) | 1983-09-14 |
JPS6248419B2 JPS6248419B2 (en) | 1987-10-14 |
Family
ID=12491252
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57037211A Granted JPS58154944A (en) | 1982-03-11 | 1982-03-11 | Signal matrix circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58154944A (en) |
-
1982
- 1982-03-11 JP JP57037211A patent/JPS58154944A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6248419B2 (en) | 1987-10-14 |
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