JPH0633700Y2 - Signal addition on / off circuit - Google Patents

Description

[Detailed Description of the Invention] [Industrial field of application] This invention selectively adds a second input signal to a first input signal to output the first input signal or the first input signal to the output end. And an improvement of a signal addition on / off circuit for providing an addition output signal of the second input signal.

[Conventional technology]

There may be a need to selectively add the second input signal to the first input signal as needed.

For example, FIG. 3 shows an example of a stereo reproducing apparatus for correcting the sound field in the room. Left and right signals L and R are input to the first and second adding circuits 1L and 1R in the positive phase. And one signal L is applied as a positive phase and the other signal is applied as a reverse phase to the third adder circuit 1. The output of the third adder circuit 1 is applied to the attenuator 5 via the time delay circuit 2, the filter 3 and the amplifier 4, and the signal level-adjusted by the attenuator 5 is supplied to the first adder circuit 1L. Are applied in the positive phase and in the reverse phase to the second adder circuit 1R, and the respective outputs are amplified by the amplifiers 6L and 6R and then reproduced by the speakers 7L and 7R.

By the way, this type of stereo playback device is
In some cases, the correction signal generated by the adder circuit 1, the time delay circuit 2, the filter 3 and the like is not always necessary. In this case, the correction signal is added to the first and second adding circuits.
It suffices to prevent application to 1L and 1R, and allow this application when necessary.

FIG. 4 shows an example of a conventional signal addition on / off circuit proposed based on such a request.
Is an input end of the first input signal, that is, the L or R signal. Reference numeral 9 is a second input signal, that is, an input terminal of the correction signal.
0, that is, the first or second adder circuit (1L or 1R)
Join in. A NPN transistor switch 11, for example, is connected between the input terminal of the second input signal of the adder circuit 10 and the reference potential point. By applying an H signal to the control input terminal 12, the second The second input signal is allowed to pass by shutting off the input signal and applying the L signal.

As a result, the output 13 of the adder circuit 10 is provided with only the first input signal or the added output of the first and second input signals.

FIG. 5 shows a specific connection diagram of the signal addition on / off circuit shown in FIG. 4, and the same reference numerals as those in FIG. 4 indicate the same parts. In FIG. 5, an operational amplifier is used as the adder circuit 10, an input signal is applied to its inverting input terminal, and the non-inverting input terminal is connected to the reference potential point. Show.

Next, the operation of what is shown in FIG. 5 will be described.
First, when the control signal applied to the control force end 12 is L, the gain from the input end 8 to the output end 13 of the first input signal and the gain from the input end 9 to the output end 13 of the second input signal If each is configured to be 0 dB, (However, R _{14 to} R ₁₇ are resistance values of the resistors _{14 to 17} , and R _Tr is impedance between the collector and emitter of the transistor 11 and R _Tr = ∞ when the control signal is L).

Further, the signals input to the input terminals 8 and 9 have a signal source impedance of 0Ω, and a signal S _{1 of 1} and a signal S ₂ of ₂ Then, the output signal S _13L of the output terminal 13 (added output of S ₁ and S ₂ ) is Then, the signals input to the input terminals 8 and 9 are added, the phases are inverted, and the result is output to the output terminal 13.

Next, when the control signal applied to the control signal input terminal 12 is H, the output signal S _13H of the output terminal 13 (only S ₁ is output) is the transistor 11 when the collector terminal signal S ₁₁ of the transistor 11 is considered.
Since the resistance value of R _TroN ≈ _0Ω , Therefore, Therefore, only the first signal input to the terminal 8 is phase-inverted and provided to the output terminal 13.

However, considering the direct current operation of the signal adder circuit shown in FIG. 4, when the transistor 11 is turned on, the saturation voltage V _{CE (Sat)} between the collector and the emitter is always generated.
The collector terminal potential V _{CE (Sat) of the} transistor 11, that is, the point B in the figure rises, and the DC potential at the output terminal of the operational amplifier 10 becomes The inconvenience that the value of changes. This state is shown in FIG. 6, and the time charts indicated by A to F show the DC potentials of the respective portions indicated by reference signs A to F in FIG. That is, when the point A becomes the H level, the point B rises to V _{CE (Sat)} as described above. C, D, E points are 0 volt, and as a result, as mentioned above, at F point A change in the DC voltage corresponding to is generated. Therefore, when the signal addition is turned on / off, the DC level changes at the output terminal 13, which causes pop noise.

[Purpose of device]

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional ones, and in which the second signal is added to the first input signal as necessary,
It is an object of the present invention to provide a signal addition on / off circuit that does not cause a change in the DC level to the output terminal when the signal is turned on / off.

[Outline of device]

In order to achieve the above object, the first aspect of the present invention is provided.
In addition to the first transistor that allows or blocks the addition of the second input signal to the input signal of, the second transistor that cancels the change in the DC potential at the output terminal is provided, It is characterized by eliminating changes in position.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First
In the figure, the same reference numerals as those in FIG. 5 indicate the same parts. To explain the difference, the phase inversion circuit 18 is connected to the input end 8 of the first input signal, and this output is connected via the resistor 14. It is applied to the non-inverting input terminal of the operational amplifier 10.

In addition, resistors 19 and 20 are provided between the non-inverting input terminal and the reference potential point.
Is connected in parallel, and the collector / emitter of the level shift switching transistor 21 is connected in parallel to the resistor 20. The base of the transistor 21 is connected in parallel with the base of the transistor 11.

Next, the operation of the embodiment of the present invention shown in FIG. 1 will be described.

First, when the level of the control signal input terminal 12 is L, the gain from the input terminal 8 to the output terminal 13 of the first input signal and the second
Assuming that the gain from the input terminal 9 to the output terminal 13 of the input signal is 0 dB, the resistors 14, 19, 20
And the resistance values of 15, 16 and 17 are R as in the example shown in FIG.
₁₇ = R ₁₄ = R ₁₅ + R ₁₆ or R ₁₉ = R ₁₆ , R ₂₀ = R ₁₅ (however, R
_{14 to} R ₁₇ and R ₁₉ and R ₂₀ are resistance values of resistors _{14 to 17} and ₁₉ , ₂₀ ), and the output signal S _13L of the output terminal 13 in this case is
Similarly to the conventional example shown in FIG. 5, the signals input to the input terminals 8 and 9 have a signal source impedance of 0Ω,
Each input signal S ₁ and S ₂ and Then, the output of the phase inverting circuit 18 of S ₁ is S ₁₈ =-
Ae ^jωt , the signal at the non-inverting input terminal of the operational amplifier 10 is Therefore, Then, the first and second signals input to the input terminals 8 and 9 are added and brought to the output terminal 13 in a phase-inverted form.

Next, when the control input terminal 12 is H, the output signal of the output terminal 13
S _13H is the collector terminal signal S ₁₁ of the first transistor 11 S
_{Because Tr} = 0 On the other hand, the signal at the non-inverting input terminal of the operational amplifier 10 at this time is Because And the output terminal with only the first input signal inverted in phase
Brought to 13.

Considering the DC operation of the signal adding circuit at this time,
The collector terminal potential of each of the first and second transistors 11 and 12 when they are on increases by V _{CE (Sat)} ,
The DC potential V _{4H at} the output terminal of the operational amplifier 10 is Therefore, the DC potential of the output terminal 13 does not change even if the transistors 11 and 21 are turned on and off.

This state is shown in FIG. 2, and the time charts indicated by A to H show the DC potentials of the respective portions indicated by the symbols A to H in FIG. That is, when the A point becomes the H level, the B and G points rise to V _{CE (Sat)} as described above. C and D points are 0 volt in terms of direct current, and at this time, E point and H point are both Will increase by a DC potential corresponding to. However, since the non-inverting input terminal and the inverting input terminal of the operational amplifier simultaneously change at the same level, the change in the DC level at the output terminal F is zero.

[Effect of the Invention] As described above, according to the present invention, there is no change in the DC level at the output end when the signal addition is turned on / off,
It is possible to eliminate the inconvenience of generating pop noise unlike the conventional one.

[Brief description of drawings]

FIG. 1 is a connection diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing DC operation of each part in FIG. 1,
FIG. 3 is a connection diagram showing an example of applying the present invention, FIG. 4 is a conceptual diagram showing an example of a conventional one, FIG. 5 is a connection diagram showing the details thereof, and FIG. 6 is a time chart showing the DC operation of each part in the figure. 8 ... 1st signal input end, 9 ... 2nd signal input end, 10 ...
Operational amplifier, 11 ... First transistor switch, 12 ... Control signal input terminal, 18 ... Phase inversion circuit, 19 ... Second transistor switch.

Claims (1)

[Scope of utility model registration request] 1. A signal adder circuit configured by an operational amplifier having a non-inverting input terminal and an inverting input terminal, configured to add and output input signals applied to the non-inverting input terminal and the inverting input terminal, The inverting input terminal is connected to a second transistor switch (11) that short-circuits the inverting input terminal to a reference potential point when switched on, and the non-inverting input terminal is connected to the second transistor switch (11). A first transistor switch (21) that is turned on / off in synchronization with the first transistor switch, and when the first transistor switch is turned on, saturation between the collector and the emitter of the first transistor switch is provided. The non-inverting input terminal by dividing the voltage into a voltage that cancels the collector-emitter saturation voltage of the second transistor switch. Signal adding on-off circuit, wherein a voltage divider is connected to be given to.