JPS58153420A - Phase locked loop - Google Patents
Phase locked loopInfo
- Publication number
- JPS58153420A JPS58153420A JP57035170A JP3517082A JPS58153420A JP S58153420 A JPS58153420 A JP S58153420A JP 57035170 A JP57035170 A JP 57035170A JP 3517082 A JP3517082 A JP 3517082A JP S58153420 A JPS58153420 A JP S58153420A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- input
- voltage
- signal
- input signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- 238000013459 approach Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
発明の技術分野
この発明はフェーズ・ロックド・ループ1llcRす”
る。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention This invention relates to a phase-locked loop.
Ru.
発明の技術的背景
フェーズ・ロックド・ループは普通位相比較器、補償フ
ィルタおよび電圧制御発振器で構成される位相帰還回路
であゆ、その構成図を第1図に示す。TECHNICAL BACKGROUND OF THE INVENTION A phase-locked loop is generally a phase feedback circuit consisting of a phase comparator, a compensation filter, and a voltage controlled oscillator, and its configuration is shown in FIG.
入力信号10と、電圧制御発振器13の出力信号14は
位相比較器11に入力され、この2つの入力信号の位相
差が補償フィルタ12を通り、電圧制御発機器taK4
1tllされることから、出力信号14の位相は入力信
号100位相とロックする。The input signal 10 and the output signal 14 of the voltage controlled oscillator 13 are input to the phase comparator 11, and the phase difference between these two input signals passes through the compensation filter 12, and the output signal 14 of the voltage controlled oscillator 13 is input to the phase comparator 11.
1tll, the phase of the output signal 14 is locked to the phase of the input signal 100.
背景技術の問題点
しかし出力信号14と入力信号100周波数が大きく噛
れていると、出力信号14は入力信号10の高調波や低
調波でロックした沙、更にはロ′ツク不可能となり、入
力信号10と無関係な発振倹することがある。Problems with the Background Art However, if the frequencies of the output signal 14 and the input signal 100 are significantly offset, the output signal 14 may be locked by harmonics or subharmonics of the input signal 10, and furthermore, it may become impossible to lock the input signal 10. There may be oscillations unrelated to signal 10.
ql!−鴫61句
この発明は上鮎の点Kliみてなされたもので、入力周
波数が大きく変化する場合でも安定にロックするフェー
ズ・ロックド・ループを提供することを目的とするもの
である。ql! - Tsuji 61 This invention was made in consideration of Kami Ayu's point Kli, and its purpose is to provide a phase-locked loop that stably locks even when the input frequency changes greatly.
発明の概要
すなわち本発明はフェーズ・ロックド・ループの電圧制
御発振器と逆の入出力特性を有する周波数電圧変換器を
設けて入力信号を周波数に対応した電圧に変換し、得ら
れた周波数電圧変換信号を低域通過フィルタを介したの
ち入力信号と電圧制御発振器出力との位相差信号と加算
し、この加算出力を電圧制御発振器に供給するようKし
たものである。Summary of the invention That is, the present invention provides a frequency-voltage converter having input/output characteristics opposite to that of a phase-locked loop voltage controlled oscillator, converts an input signal into a voltage corresponding to the frequency, and converts the resulting frequency-voltage converted signal. is added to the phase difference signal between the input signal and the voltage-controlled oscillator output after passing through a low-pass filter, and the added output is supplied to the voltage-controlled oscillator.
発明の実施例
以下図面を参照して詳細に説明する。第211はこの発
明の一実施例を示すものである。入力信号20は位相比
較821と周a、敏電圧変換a2BK加えられる。位相
比較器21の出力は加算器22と補償フィルタ23を通
や電圧制御発振1)24に入力され、この出力信号27
は前記位相比較器21のもう一つの入力となり、帰li
ループを構成している。一方間波数電圧変換器25の出
力は低域通過フィルタ26を通や加算器22に入力され
る。ζこで周波数電圧変換器25の入出力特性は電圧制
御発@924の入出力特性と逆の**を持つものとする
。つまり周波数電圧変換s25の出力を電圧制御発振器
24に入力し九場合には、周波数電圧変換器25の入力
信号周波数と電圧制御発振器24の出力信号局波数が同
じくなる関係を、周波数電圧変換器25と電圧制御発振
器24は持つものとする。Embodiments of the invention will now be described in detail with reference to the drawings. No. 211 shows an embodiment of the present invention. The input signal 20 is subjected to a phase comparison 821 and a voltage conversion a2BK. The output of the phase comparator 21 passes through an adder 22 and a compensation filter 23 and is input to the voltage controlled oscillation 1) 24, and this output signal 27
is another input of the phase comparator 21, and the return li
It forms a loop. On the other hand, the output of the interwave number voltage converter 25 is input to the adder 22 through a low-pass filter 26 . ζ Here, it is assumed that the input/output characteristics of the frequency-voltage converter 25 are reverse to the input/output characteristics of the voltage control generator @924. In other words, when the output of the frequency-voltage converter s25 is input to the voltage-controlled oscillator 24, the frequency-voltage converter 25 establishes a relationship in which the input signal frequency of the frequency-voltage converter 25 and the output signal station frequency of the voltage-controlled oscillator 24 are the same. It is assumed that the voltage controlled oscillator 24 has the following.
次に入力信号20と出力信号27の周波数が大きく噛れ
ている場合に、フェーズ・ロックド・ループがロックす
る動作を説明する。Next, a description will be given of an operation in which the phase-locked loop locks when the frequencies of the input signal 20 and the output signal 27 are largely offset.
第3図は本発明における位相比較821の出力を示す屯
のである。入力信号20は位相比較器21に入力され、
その出力は加算$22.補償フィルタ23を通じて電圧
制御発振器24に加わる。FIG. 3 shows the output of the phase comparator 821 in the present invention. The input signal 20 is input to a phase comparator 21,
Its output adds up to $22. It is applied to a voltage controlled oscillator 24 through a compensation filter 23.
しかし入力信号20と出力信号27の周tlLaが大き
く噛れている場合には、位相比較器21の出力28は第
3図に示すように高い周波数で正負の間を往復する。よ
ってこの出力28は加算器22と補償フィルタ23を通
過すると、補償フィルタ23の高kaP波特性によ抄微
少な信号となり電圧制御発振器に与える影響はほとんど
なくなる。一方間波数電圧交換器25の出力は、低域通
過フィル126と加算器22、補償フィルタ23を通じ
て電圧制御発振器24に加えられるのでその出力信号局
波数は入力信号20の周波数に近づいてゆき、ついには
フェーズ・ロックド・ルーズのキャプチャーレンジに入
り、ロックされるわけである。However, if the frequencies tlLa of the input signal 20 and the output signal 27 are largely offset, the output 28 of the phase comparator 21 reciprocates between positive and negative at a high frequency, as shown in FIG. Therefore, when this output 28 passes through the adder 22 and the compensation filter 23, it becomes a very small signal due to the high kaP wave characteristics of the compensation filter 23, and has almost no influence on the voltage controlled oscillator. On the other hand, the output of the wave number voltage exchanger 25 is applied to the voltage controlled oscillator 24 through the low pass filter 126, the adder 22, and the compensation filter 23, so the output signal station wave number approaches the frequency of the input signal 20, and finally enters the phase-locked-loose capture range and becomes locked.
低域通過フィルタ26は、フェーズ・ロックド・ループ
がロックされた場合1周波数電圧変換器25の出力の高
域成分をフィルタし、41#還ループの高域特性に、周
波数電圧変換825の影響を与えないためのものである
。The low-pass filter 26 filters the high-frequency component of the output of the 1-frequency voltage converter 25 when the phase-locked loop is locked, and eliminates the influence of the frequency-voltage converter 825 on the high-frequency characteristics of the 41# return loop. It is meant not to give.
発明の効果
このよ5KL、てフェーズ・ロックド・ルーズがロック
していない状態から安定にロックすること−が可能とな
る。また入力信号周波数が急激に変化し、ロックがはず
れた状態からも同様にして再び安定にロックすることが
可能となる。まえ本発明は電圧制御発振器24の代わシ
にモータを用いても同じ効果が得られる。電圧制御発振
器やモータは一般に入力電圧と発振周波数の関係が線形
となっているので周波数電圧変換器には線形のものが使
えることも利点である。Effects of the Invention With this 5KL, it becomes possible to stably lock the phase locked/loose from an unlocked state. Furthermore, even if the input signal frequency suddenly changes and the lock is lost, it is possible to stably lock it again in the same way. In the present invention, the same effect can be obtained even if a motor is used in place of the voltage controlled oscillator 24. Since voltage controlled oscillators and motors generally have a linear relationship between input voltage and oscillation frequency, it is also advantageous that a linear frequency-to-voltage converter can be used.
第4@は本発明の他の実施例である。この例では補償フ
ィルタ23は位相比較器21のすぐ後に位置しているが
、この場合にも同様の効果が得られる。The fourth @ is another embodiment of the present invention. In this example, the compensation filter 23 is located immediately after the phase comparator 21, but the same effect can be obtained in this case as well.
11図は従来の7エーズ・ロックド・ルーズの構成図、
第2図は本発明の一実施例の構成図、第3図は本発明の
一実施例における位相比較器の出力信号波形、第4図は
本発明の他の実施例である。
10・・・入力信号、11・・・位相比較器、12・・
・電圧制御発振器、14・・・出力信号、20・・・入
力信号、21・・・位相比較器、22・・・加X器、2
3・・・補償フィルタ、24・・・電圧制御発振器、2
5・・・周波数電圧変換器、26・・・低域通過フィル
タ。
代理人 弁理士 則 近 麿 佑
(ほか1名)
第1図
第2図
第3図Figure 11 shows the configuration of the conventional 7A's locked and loose system.
FIG. 2 is a block diagram of one embodiment of the present invention, FIG. 3 is a waveform of an output signal of a phase comparator in one embodiment of the present invention, and FIG. 4 is another embodiment of the present invention. 10... Input signal, 11... Phase comparator, 12...
・Voltage controlled oscillator, 14... Output signal, 20... Input signal, 21... Phase comparator, 22... X adder, 2
3... Compensation filter, 24... Voltage controlled oscillator, 2
5... Frequency voltage converter, 26... Low pass filter. Agent: Patent attorney: Yu Chika Maro (and 1 other person) Figure 1 Figure 2 Figure 3
Claims (1)
得られ先位相差信号を補償フィルタを介して電圧制御発
振器に供給するようkしたフェーズ・ロックド・ループ
において、前記電圧制御発機器と逆の入出力特性をもつ
周波数電圧変換器を設けて前記入力信号を周波数に対応
し九電圧に変換し、得られ九周波数電圧変換信号を低域
通過フィルタを介し九のち前記位相差信号と加算するよ
うにしたことを特徴とする7エーズ・ロックド・ループ
。In a phase-locked loop, the phases of an input signal and an output signal of a voltage-controlled oscillator are compared and the obtained phase difference signal is supplied to a voltage-controlled oscillator via a compensation filter. A frequency-to-voltage converter with opposite input/output characteristics is provided to convert the input signal into nine voltages corresponding to the frequency, and the resulting nine-frequency voltage conversion signal is passed through a low-pass filter and then added to the phase difference signal. 7 A's Locked Loop.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57035170A JPS58153420A (en) | 1982-03-08 | 1982-03-08 | Phase locked loop |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57035170A JPS58153420A (en) | 1982-03-08 | 1982-03-08 | Phase locked loop |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58153420A true JPS58153420A (en) | 1983-09-12 |
Family
ID=12434383
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57035170A Pending JPS58153420A (en) | 1982-03-08 | 1982-03-08 | Phase locked loop |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58153420A (en) |
-
1982
- 1982-03-08 JP JP57035170A patent/JPS58153420A/en active Pending
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