JPS58150310A - Device for regulating one or both of amplitude and dc level of input analog signal - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for calculating an analog signal applied to the input of an analog-to-digital (A-D") converter in relation to the low and high level limits to which that converter responds. The invention relates to a device for adjusting the amplitude and/or DC level of an input analog signal by adjusting the amplitude and/or DC level of the input analog signal. The present invention is particularly concerned with the amplitude of an analog signal, or its maximum and minimum levels (in this case the average D).
a variable gain amplifier or DC level control circuit (referred to as C level or simply DC level), or both, through which the received analog signal is passed before being applied to the converter.
It is particularly useful in a scheme for adjusting with respect to the limits of the input of an A/D converter by controlling (or both) the input limits of an A/D converter.

The analog-to-digital converter produces, over the observed time length of the analog signal, a digital word having a value representing the amplitude of the samples of the input analog signal sampled over that time length. Ideally, the amplitude and average DC level range of the analog signal does not change over time, and the transducer is such that the expected sampled amplitude of the analog signal is at the low level limit of the input range of the transducer and It is designed to be within (match) the high level limits and for example to center the range of its low and high level limits at the expected average DC level of the analog signal. Under these conditions, the transducer produces a digital word (
For example, it is not necessary to generate all 0's or all l).

A method of adjusting the amplitude of an analog signal to a value smaller than the ideal method in order to match the analog signal to one of the limits of the signal range to which the A/D converter responds costs $97
Corllhill dated 30th March 2006.
) et al., U.S. Pat. No. 3.94F.806. In this patent specification, A-D
An automatic gain control circuit (AG
An A-to-D converter with a C circuit) is shown. This device matches the maximum amplitude of the analog signal to the upper limit of the input range of the converter, but when the consistently occurring maximum value of the analog signal amplitude falls below the lower limit of the input range of the converter, the amplitude of the analog signal cannot be increased. The apparatus shown in the above patent specification is also responsive to each maximum digital word taken from the analog signal whose amplitude equals or exceeds the upper limit of the input range of the transducer, so that the AGC circuit response to any isolated analog signal sample that is equal to or exceeds the upper limit of the input range of . Furthermore, this device does not include means for controlling the average DC level of the analog signal supplied to the A-D converter.

As discussed here, the amplitude of the average analog signal is A-
If the input limits of the D-converter are not met, the value of the digital word produced by the A-D converter can drop to a minimum value (i.e., all 0s) and also to a maximum value (i.e., all 1s). It can increase. It is an object of the present invention to determine the amplitude of an analog signal in relation to known lower and upper limits of the range of signals to which this A-D converter responds by determining the value of the digital word produced by the A-D converter. The objective is to calculate the Such calculations then allow adjustments to be made to the analog signal amplitude or average DC level, or both.

More specifically, in accordance with the illustrated embodiment described below, the present invention provides for converting one or both of the amplitude and DC level of the input analog signal provided to the input terminal (70) to the analog-to-digital converter (12). first means (7) for amplifying the received input analog signal and supplying it to the input (14) of said analog-to-digital converter;
2,6B, 76.80) and the analog-to-digital converter (between one output (l@) and the control terminal means (C1 of 69 or child terminal of 80) of the first means for amplification. Combined detection means (+8, button, button, 46.42.48
), said analog-to-digital converter (l''4 is responsive to an amplified signal applied to its input (+4) from said first means to convert said amplified signal The first means generates a series of digital output words having values that are a function of the samples of the signal;
said control terminal means for controlling said amplified signal applied to an input θ of said digital converter θ; performing a first count of digital words having a first value representing the analog-to-digital converter (1'4) and performing a second count of digital words having a second value representing the lower limit of the input range of and means for detecting a control signal (such as HPXLP) indicative of first and second occurrences of first and second counts reaching predetermined first and second numbers, respectively. generates. r more,
A control means (50, 52, 56, 6, 66) is connected between the detection means and the control terminal of the first means for amplification.
．． 78) are coupled, said control means responsive to a control signal from said detection means to generate a control signal for application to a control terminal of said first means for amplification.

The apparatus of the invention is useful for adjusting the limits of an analog signal to approximate the upper and lower limits of an A-to-D converter, or for adjusting the DC level of an analog signal to some desired level within the input limits of an A-to-D converter. It can be implemented in an AGC device to modify the amplitude of the analog signal or its DC level in order to adjust the point.

Hereinafter, a detailed explanation of the present invention will be given with reference to the figures.
The conversion circuit 12 has an input signal terminal S coupled to the input terminal 4. - By way of example, the A-D conversion circuit 12 outputs all logic values 0 to 10 for inputs lower than 11 millivolts at output terminal 0 connected to output terminal 16 of the device.
It is described as a 6-pit device that generates 6-bit words ranging all the way to logic 1's for an input of 0 millivolts. A
-D conversion circuit 12 is a multiplex cable (at least 6 lines)
High peak detection circuit 1 and low peak detection circuit 2 through
0. Multiplex cables are indicated by slash (1) lines such as 22. Tarokk source 24 is A
It is coupled to each clock (0) terminal of the -D conversion circuit 12, high peak detection circuit 18, and low peak detection circuit 20.

On the occurrence of each clock pulse, such as 26, the A/D converter circuit 12 generates a 6-pit word having a value representative of the amplitude of the voltage signal being applied to the terminal 14. Regarding the 6-bit A/D converter circuit shown in the example, if the output signal from the A/D converter circuit 12 includes six 11's, then the output signal from the six input NAND gates and the timing circuit is The high peak detector 18 generates an instantaneous logic 0 pulse as shown at 28 and, when necessary, a logic level signal. If the signal produced by A-to-D conversion circuit 12 contains six '0's, a low peak detection circuit similar to peak detection circuit 18 except that it contains six input NOR gates is used. One circuit day consists of six 0s (
(instead of six 1's) in response to an instantaneous logic 0 pulse as shown at 30, and otherwise produces a logic level signal.

Detection circuit 18 is coupled to the count A terminal of first incrementing counter 40 . The counter 40 is connected to a high peak double threshold detection circuit 42 having two output terminals HP and a door. Detector 42 operates according to rows I and 2 of table 2 shown in FIG. 2, as will be explained in more detail below. Detector 42 is essentially a comparator that compares the count contained in counter 40 at a given time with a preselected set of high and low numbers, and a gate that generates the output signals shown in Table l. It consists of a logical device including:

Similarly, detector 2o is coupled to a second incrementing counter 46, which in turn is coupled to a low peak detector 48. Detector 4 operates according to rows 3 and 4 of table l of FIG.
It has a similar structure to 2.

The output HP of detector 42 is connected to AND gates 50 and 52.
and its output face is coupled to one input of AND gates 54 and 56. The output LP of detector 4 is coupled to the second input of AND gates 50 and 56, and the output LP of AND gate 5
2 and 54 second inputs. The update control circuit 60 connects the tarok input terminals C of the detectors 42 and 48.
It is connected to the counter 40 through a short continuous line.
and 46 reset input terminals R1 and goo) 50
．． 52, 54 and 56, respectively. As will be explained in more detail below, at a suitable point the circuit 6o generates an instantaneous pulse as shown at 62 and clocks the counts of the counters 40 and 46 into the detectors 42 and 48, respectively. counter 4
Reset 0 and 46. At the same time, the signals generated by detectors 42 and 4 are energized by pulses 62 as shown in Table 2 of FIG.
One of 50, 52, 54 and 56 can be activated.

This will be explained in more detail later. AND gates 50 and 54 are coupled to the up inputs UP, down inputs DN of a third up/down binary counter 64. AND gates 52 and 56 are coupled to the inputs IJP, DNK of a fourth up/down binary counter 66.

Counter 64 is coupled via multiple cables to control terminal C of binary weighted switched attenuator 68. The input signal terminal F0 of the device, to which the analog signal to be digitized is supplied, is coupled to a current buffer 72. The output of current buffer 72 is coupled to the signal input of attenuator 68 of the automatic gain control circuit. The automatic gain control circuit comprises, in addition to the attenuator 6, a counter 64 and a fixed gain amplifier 76 to which the output of the attenuator 68 is coupled. Attenuator 6
8 typically has a damping ratio of 3:1.

As the counter 68 is incremented by the signal passing through the AND gate 50, the attenuation of the attenuator 68 is increased, reducing the peak-to-peak amplitude of the signal passing through the amplifier 76, thereby increasing the attenuation of the attenuator 68. The gain measured from the input to the output of amplifier 76 is reduced. Contrary to the above, when the count value of the counter 64 decreases due to the signal from the AND gate 54, the attenuation degree of the attenuator 6 decreases, and the peak value of the signal passing through the amplifier 96 decreases.
Increase peak amplitude. Generally, the counter 64- is 6
64 is a counter, so this counter 64 is 64.
It is possible to set one of four damping ratios one after another.

Counter 66 is coupled to a digital-to-voltage converter 78, which is also coupled to the (+) terminal of operational amplifier 80. Operational amplifier (→
The terminal is coupled to receive a signal from amplifier 76. The output of amplifier 80 is terminal! 4 to the input of the A-to-D converter 12.

The analog-to-digital converter of FIG. 1 converts amplitude changes of a predetermined constant duration into a terminal 70, such as a series of analog signals representative of a series of frames of information from a television camera. It is designed to operate on a range of analog signals. The input signal is amplified by an amplifier (amplifier) 6, offset in amplitude by an amplifier 8o in a manner to be described later, and supplied to an input terminal 14 of an A/D converter 12. And this A-D converter 1
2. The input signal is digitized.

The operation of the circuit of FIG. 1 is as follows. This is the (a) terminal! 4 is supplied with an analog signal having the same constant duration as the input analog signal supplied to terminal 70;
(b) Assume that the signal applied to terminal 14 may be modified in peak-to-peak amplitude and average DC level with respect to the input analog signal as explained below. Before the analog signal is applied to terminal +4, the pulses 62 from update control circuit 6o lead the counts in counters 40 and 46, respectively, to voice detectors 42 and 48, respectively, and for reasons to be explained later, are
50, 52, 54 and 56, and also resets counters 40 and 46.

The clock source 24 generates pulses at a predetermined constant frequency of, for example, 4.8 MHz. These tarok pulses are A
-D converter 12, which generates a 6-bit digital word in response to this clock pulse. Not necessarily, but generally a terminal! The portion of the analog signal supplied to 4 is of sufficiently high amplitude that the A/D converter 12 generates several output words of 6 logic 1 bits. Similarly, although not necessarily required, the portion of the analog signal applied to terminal 14 is typically sufficient to cause A/D converter 12 to generate an output word of some number of six logic zero pits. It is assumed that the amplitude is low. If the signal applied to terminal +4 is related to the signal generated by a TV camera, the 6 logic I states correspond to very bright parts of the scene, and the 6 logic 0 states correspond to very bright parts of the scene. corresponds to the dark area.

For each output signal consisting of all logic 1 bits from ADC 12, detector 18 generates a logic 0 pulse 28 under timing control of clock source 24. For each output signal of all logic O bits from the A/D converter 12, the detector 20 generates a logic zero pulse 30 under timing control of the clock source 24.

Counter 40 counts the number of pulses generated by detector 18 with all logic ones, while counter 46 counts the number of pulses generated by detector 20 with all logic O's. As previously mentioned, for an analog signal of predetermined duration and a tarok pulse of constant frequency provided by clock source 24, the A-to-D converter! The total number of digital words generated by 2 is known in advance. A-D converter! When provided with any signal for which it is desired to use the full operating range of 2, a small fraction or portion of the total number of such digital words are all logical! and the sub-parts or portions should all be logical zeros. If all 1's do not occur, and only all 0's occur, then the full digital range of A/D converter 12 is not utilized. Similarly too many all logical! The occurrence of words and all logic 0 words causes the A-to-D converter to saturate and create distortion in any use of the digital words produced by the A-to-D converter 12. TV mentioned earlier
When using a camera, experience has shown that the most desirable images are obtained when the frame contains 0.5% to 1.5% of all logic 1s and 1% to 2% of all logic 0s. Ta.

Since the number of words generated by the analog-to-digital converter for such a series of analog signals is known and constant, the numbers representing the various percentages are also known; The data is stored in each detector 42 and 4 by wiring such as in a decoder or memory.

- As an example, assume that each analog signal is digitized by the A-D converter 12 into 1 oooO word.

Detector 42 thus stores values 5 and 15, and force detector 4 stores values 10 and 20. After the illustrative analog signal is applied to terminal 14 and digitized, and before the next analog signal is generated, 62 such initial pulses are generated to clock the value of counter 40 to detector 42. and the value of the counter 46 is derived on the detector 4th. Then, counters 4o and 46 are incremented.

The detector 42 converts the number from the counter 40 into a fraction O1.
Compare with numbers representing 5 percent and 1.5 percent. Using values 5 and 15, the table in Figure 2!
Referring to , if the count of counter 40 is too high, ie greater than 15, terminal HP is set to a logic level and terminal OK is set to a logic 0 level K-. Also, if the count of the counter 40 is not high enough, i.e. less than 5, the terminal is logic! level, and terminal HP is set to a logic 0 level. Otherwise both HPXπ are set to a logic 0 level.

Detector 4th and counter 46 are tables! It works the same way according to line 3.4 of . After the above-described operations have taken place within the detector 42 and within four days, a pulse 62 from the update control circuit 60 energizes AND, 52, 54, and 56. The particular AND gate, if any, to be activated (at most only one AND gate is activated) is determined according to Table 2. For example, if both HPXLP are logic 1 (row 2 of Table 2), gate 50 is activated and the A-D converter! 2 indicates that there are too many analog signals outside the upper and/or lower limits that can be handled. In this case, according to row 2 of table 2, counter 64 (which can be assumed to have been initially set to some arbitrary count value between its upper and lower limits by the previous modification condition) is advanced by l.

Thereby the attenuation of attenuator 6 is increased and the attenuation of amplifier 7 is increased.
The amplitude of the output of 6 is reduced and the gain of the circuit consisting of the attenuator 6 and amplifier 76 combination is reduced. Therefore, when the next analog signal is applied to terminal 70, the amplitude of the signal appearing at terminal 14 will be reduced relative to the amplitude of the preceding analog signal. The assumption is that there is no change between one analog signal and the next, or that said change is small, as is the case with successive frame signals, typically generated by a TV camera. If gate 54 is energized more than gate 50 (HP = logic 1, ■ = logic), the signal at terminal 14 will contain no or very little high and low peaks. Therefore, the counter 64 is decremented by l, the attenuation of the attenuator 6 is less, and the amplitude of the signal at the output of the amplifier 76 is greater than the previous analog signal at the terminal 70. It is increased so that it is amplified by the gain.

If gate 52 is activated, the DC offset of the analog signal is too large and more than 1.5 percent of the digital signal from A/D converter 12 is all logic! And A-
This means that less than one percent of the total words from D-converter 12 are all logic zeros.

Counter 66 is thereby incremented by I, the output voltage of converter 78 is reduced, and amplifier 80 is varied to reduce the DC offset applied to the subsequent signal applied to terminal 70. Finally, when gate 56 is energized, the analog signal offset, C offset, is so small that less than 0.5 percent of the digital words provided by A-to-D converter 12 are all logic ones, and the A-to-D conversion This means that 2 percent or more of all words supplied from device I2 are all logical zeros. Therefore, the counter 66
is decreased by one, the output voltage of the converter 7 is increased, and the amplifier 80 is modified to provide a larger C offset to the subsequent signal applied to terminal 70.

If the condition continues for the next analog signal applied to terminal 14 (i.e., if the peak of the signal -
The peak amplitude is very high for a very long period of time, or
(or if the DC offset is inadequate), the appropriate one of the gates 50-56 is re-energized and one of the counters 64 or 66 continues until no gate is energized. It is further increased or decreased after each successive analog signal applied to terminal '70. Counters 64 and 66 are both of a type that does not increase beyond their upper limit count or decrease beyond their lower limit count. Therefore, if the signal is outside the range of signals processed by the device, a distorted signal will be generated from the A/D converter 2. For purposes of explaining the invention, it will be assumed that the nature of the signal applied to terminal F0 and the arrangement of the apparatus are set such that no distortion conditions occur.

Then neither gate is energized (row of table 2!
, 6.7.8.9) Explain the state. Row l is all logical O and all logical! , and amplifiers 76 and 80 are properly adjusted. That is,
The signal supplied to terminal 14 is neither large nor small;
It is also adjusted so that it is not offset to an undesirable state. Lines 6, 8, and 9 show that the signal supplied to the A-to-D converter 12 is such that the A-to-D converter generates too many and too few all logic 1 digital words, and It illustrates conditions that generate too many and too few digital words that are all logic zeros. For the condition indicated by row 1 of Table 2, the series of analog signals 2, 'counter' until a change in content occurs to an extent that requires one or both of amplifiers 76 and 80 to be readjusted as described above. 64 and 6
None of the values of 6 change.

In the situation represented by rows 6 to 9 of table 20,
No action is taken. However, (a) a condition in any one of these rows exists and the signal changes to a new amplitude, or to a new average level centered around the DC offset of the output of amplifier 80, and therefore Table 2 (b) whereby the converter converts the output of the A-D converter 12 into the operating state as described above in row 1 of Table 2.
, 6.7.8 and 9.

Although the A/D converter of FIG. 1 is designed and described for situations in which the input analog signal appears as a series of burst signals, the device is
a) supplying the detectors 42 and 48 with the actual number of words generated by the A-D converter 12; and (b) actually calculating the percentage periodically, such as when the input pulse 62 occurs. By providing such a detector it is also possible to operate in conjunction with continuous input.

As another variation, the preset numbers in detectors 42 and 4B may be chosen to represent a tolerance limit for a plurality (eg, 1000) of words provided by A/D converter 12. Under such conditions, A-
A color/counter (not shown) can be used to count the number of words produced by the D-converter 12, and when that count is reached, the output of the counter is triggered by a pulse 62.
can be used to generate.

The gist of the invention is as shown in the claims, but it goes without saying that the invention described in the claims also includes the following embodiments.

(1) detecting means, in response to first and second count values reaching first and second predetermined numbers, respectively, first and second counts representing occurrences of the first and second numbers of digital words, respectively; generating a third control signal (HP, LP) and in response to not reaching the first and second predetermined numbers, respectively; The second and fourth signals (HPX
LP), and the control means is responsive to the first to fourth control signals.

(2) The detection means includes (1) a high peak detector (+81, an accompanying first increment counter (40) and a second high peak threshold detector (42), and (b) a low peak detector - , an associated second incrementing counter (46) and a second low peak threshold detector (48), the inputs of the high peak detector and the low peak detector being coupled to the output of the analog-to-digital converter. and a high peak detector and a low peak detector respectively input the respective digital values of the first and second values generated by the analog-to-digital converter to the respective inputs (A) of the first and second counters. a high peak threshold detector (42) and a low peak threshold detector (46) are operative to provide a signal for incrementing the counter in response to the first and second counters; and the second count value are compared with the first and second predetermined values, respectively, and the first, second, third and fourth signals (HP, HP,
The apparatus according to fl) above, which operates to generate LP,, π).

(3) The amplification means is a switching attenuator (
6 days), and the control means includes the first and second days) (5 days).
0,54) and the first up-down counter (e4)
The first and second gates are configured to receive first and third signals (HP, LP) and second and fourth signals (HP, LP) supplied from a high peak threshold detector and a low peak threshold detector, respectively. W, LP), and when energized, (1
) When both peak threshold detectors generate signals (HP and LP) representing the occurrence of the first and second number of digital words, the up-down force generates a signal that increases the count of the counter. ) when both peak threshold detectors produce a signal ("π") indicating the absence of occurrences of the first and second number of digital words.
The control means (C) of the switching attenuator (6 days) is coupled to the output of the up-down color/response to generate a signal that decreases the count of the counter and is responsive to the count value of the analog-to-digital Apparatus according to (2) above, operative to control the amplitude of an analog signal supplied to the input of the converter.

(4) The amplifying means includes further means () responsive to a control signal supplied to the input (→) for adjusting the DC level of the amplified signal supplied to the input of the analog-to-digital converter.
80), the control means (52, 56, 66, '78) being coupled between the detection means and the input of said side means;
and (b) adjusting the DC level of the amplified signal in response to the second signal toward the low level limit of the input of the analog-to-digital converter; The device according to (1), (2) and (3) above, characterized in that the DC level of the signal is adjusted towards the high level limit of the input of the analog-to-digital converter.

(5) The said side means include an operational amplifier (80) to which an amplified signal is supplied to one input (→), and this operational amplifier controls its output according to the level of the signal supplied to the other input. generating an amplified signal having a reference (pace) level to be measured and feeding it to an analog-to-digital converter;
(52, 56), second up-down counter (6
6), and a digital-to-voltage converter (Ma8),
The third gate is fed by the high and low peak detectors respectively! and a fourth signal (HP, π), the fourth gate responds to a second
The output of the second up-down counter (66) is fed to a digital-to-voltage converter (matrix 8). The digital-to-voltage converter generates a voltage at its output at a level according to the count value of the second up-down counter, and the output voltage from the digital-to-voltage converter is converted to an operational amplifier (8
The device according to (4) above, characterized in that the device is configured to be supplied to the other input (-1) of 0).

(6) An update control means (60, D) is provided which operates at the end of a predetermined time length, and this update control means operates each peak threshold value detector to 4 signals and then energizes the gates of the first and second incrementing counters (40, 46).
The above (
10) or the device described in (5).

[Brief explanation of drawings]

FIG. 1 shows a preferred embodiment of a device for adjusting the amplitude and/or DC level of an input analog signal according to the present invention in the form of an electric circuit block diagram; FIGS. Learn more about the operation of some of the circuits in the device shown in Figure 1! l'lJ is a diagram showing a table that is not easily explained. +2... Analog-digital converter, 7o... Input terminal, 68 C180 (+)... Control terminal, 14
...Input of converter 12, +6...Output of converter 12,

Claims (1)

[Claims] ++1 An apparatus for adjusting the amplitude and/or DC level of an input analog signal in relation to upper and lower limits of an input range of an analog-to-digital converter, the apparatus comprising: amplifying a received input analog signal; , a first hand μ for supplying the input of said analog-to-digital converter; and a detection coupled between the output of said analog-to-digital converter and the control terminal means of said first means for amplification. means, wherein said analog-to-digital converter is responsive to an amplified signal provided at its input from said first means to set at said output a value that is a function of the samples of said amplified signal. said first means has said control terminal means for controlling said amplified signal applied to an input of said analog-to-digital converter; said detecting means performs a first count of digital words having a first value representing the upper limit of the input range of the analog-to-digital converter and a second value representing the lower limit of the input range of the analog-to-digital converter. means for performing a second count of the digital words held; A control means is coupled between the detection means and a control terminal of the first means for amplification, and the control means generates a control signal indicative of the occurrence of the detection. a first for said amplification in response to a control signal from said means;
apparatus for adjusting the amplitude and/or direct current level of an input analog signal for generating a control signal for supply to a control terminal of a means for adjusting the amplitude and/or direct current level of an input analog signal;