CA1197320A

CA1197320A - Adaptive analog-to-digital conversion method and system

Info

Publication number: CA1197320A
Application number: CA000413702A
Authority: CA
Inventors: Joseph F. Schanne; Lewis D. Elliott
Original assignee: RCA Corp
Current assignee: RCA Corp
Priority date: 1981-10-30
Filing date: 1982-10-19
Publication date: 1985-11-26
Also published as: DE3240175A1; FR2515898A1; IT8223965A0; GB2110490B; FI823616L; KR840002173A; ES516742A0; ES8400638A1; GB2110490A; JPS5884530A; FI823616A0; FR2515898B1; IT1153604B; JPS58150310A; SE8206124L; SE8206124D0; AU8971182A

Abstract

ADAPTIVE ANALOG-TO-DIGITAL
CONVERSION METHOD AND SYSTEM

Abstract A system (FIG. 1) includes a conventional N bit analog-to-digital converter (12) and also includes a variable gain amplifier (68, 76) and DC offset control circuit (80) to adjust the amplitude and DC level of a received analog input signal prior to its application to the converter. In order to assure use of the full N bit capacity of the converter, without regard to the amplitude and DC level of the received analog input signal, the number of lowest value (all 0's) and the number of highest value (all 1's) words produced by the converter are compared to respective threshold values and, on the basis of those comparisons, signals are generated for controlling the variable gain amplifier and the DC level control circuit.

Description

32~

-1 RCA 75, 993 ~OP.PI'IVE ANALOG~TO~DIGITAL CONV:ERSION
METHOD AND SYSTEM
This invention relates to assessing an analog signal, which is being applied -to the input of an analog-to-digital (A/D) converter in terms of the low level and high level limits -to which the convexter responds, where -the amplitude of the analog signal (as measured ~y the signal's maximum and minimum values) may vary with time. The invention is particularly useful in a system where th~ analog signal's amplitude or the average of its maximum and minimum leve!ls (herein referred to as average DC level or simply DC level), or both, is (or are~
adjusted with respect -to the limits of an A/D converter input, by controlling a variable gain amplifier or a DC
level control circuit (or both) through which a received analog input signal is passed prior to its application to the converter.
An A/D converter produces, over an observed time length of an analog signal, digital wor~s whose values represent the amplitudes of input analog signal samples taken throughou-t that -time length. Ideally, ranges of the amplitude and average DC level of the analog signal do not change over time, and the con~erter is designed so that the sampled ampli-tudes of the expected analog signal lie within ~match) the low and high limits of the converter input range, and so that (for exa~ple) the center of the range's high and low limits is ak the expected average DC
level of the analog signal. Under such conditions, the converter is not called upon to produce a digital word of value (for example, all O's or all l's3 to represent an ana].og signal sample lying below or above a limit of the inpuk range of -the converter.
An appxoach to adjusting ana:Log signal amplitude in a less than ideal system, in order to match the analog signal to one of the limits cf the signal range to which the A/D converter responds, is shown in United States Patent No. 3,947,806 to Corkhill et al. issued March 30, 1976. That patent shows an A/D converter with an ~!

3~C~

-2- RCA 75,993 automatic gain control (AGC) circuit which adjusts, upwardly or downwardly, the amplitude of the analog signal applied to the A/D converter in accordance with the value of the most siynificant bits of words produced by the A/D
converter. While that system tends to match maximum amplitude of the analog signal to the upper limit of the conver-ter's input range, the sys-tem is incapable of increasing the ampli-tude of the analog signal when consistently~occurring maxima in the analog signal amplitude drop below the lower limit of the input range of the conver-ter. Further, the system shown in the patent responds to each maximum value digital word (which is derived from an analog signal sample whose amplitude is equal to or exceeds the upper limit of the converter input range)~ so that the AGC circui-t responds to any isolated analog signal sample which equals or exceeds the upper limit of the converter input range. Still further, that system makes no provision for controlling the average DC
level of the analog signal applied to the A/D converter.
As viewed here, the values of diyital words produced by an A/D converter may drop to minimum (e.g., all O's) and may rise to maximum value (all l's), when the average analog signal amplitude is not ma-tched to the limits of the A/D converter input. It is the purpose of ~5 the present invention to assess the amplitude of the analog signal in terms related to the known low and high limits of the range of signals to whioh the A/D converter responds by assessing the values of the digital words produced by the A/D converter. Such assessment, in turn/
allows for adjustment of amplitude or average DC level (or both) of the analog signal.
In more formal terms, the present invention is directed to a method for assessing one of or both amplitude and base level occurring in a given length of time of an analog signal, where the assessment is made in terms o low aIld high level limits of response range of an A/D converter to which the analog signal is applied. As in the prior art, the present method includes the step of

3~

~3~ RCA 75,993 detectin~, throughou-t the given time length, the occurrence of digital words of value representing one of the limits of the A/D converter within a series of digital words, which series is produced by the A/D converter throughout the given time length.
According to the invention, the detecting step comprises: (a~ detecting within the given time length:
both (i) an occurrence of a first number of digital words within the series having a first value (for example, all l's) representing the high limit of the A/D converter response range, which first number equals or exceeds a first threshold value, and (ii) an occurrence of a second number of digital words within the series having a second value (in this example, all O's) representing the low limit of the A/D converter response range, which second number equals or exceeds a second threshold value; so that (b) at the end of -the given length of time the detected first and second occurrences provide the desired assessment of the analog signal.
The inventive analog signal assessment method may be used in an AGC method to modify the analog signal's amplitude or its DC level to adjust the limits of the analog signal to approximate the upper and lower limits of the A/D converter or to adjust the analog signal DC level to some desired point within the input limit range of the A/D converter.
In the drawing:
FIGURE 1 is an analog-to-digital con~erter system in electrical block diagram form in accordance with a preferred embodiment of the present invention; and FI~URES 2 and 3 are tables useful in understanding the operation of certain circuits of the FIGURE 1 A/D converter.
Referring now to FIGURE 1, a conventional analog-ko-digital (A/D) converter circuit 12 has an input signal (S) terminal coupled to an input terminal 14. By way of example, A/D 12 may be a six-bit device producing, at its output terminal (O) connected to system output ~4~ RCA 75,993 terminal 16, six~bit "words" ranging from all logic 0's fox an input of less than 11 millivolts to all logic l's for an input of 700 millivolts. A/D 12 is coupled via a multiconductor cable (at least six~ to a high peak detector circuit 18 and to a low peak detector circuit 20.
A mul-ticonductor cable is indicated by a slash (/) line such as 22. A clock source 24 is coupled to the clock ~C~
terminal of each of A/D 12, hig:h peak detector 18 and low peak detector 20.
Upon the occurrence of each clock pulse such as 26, A/D 12 produces a six-bit word having a value which represents the amplitude of the voltage signal being applied to terminal 14. For an exemplary six-bit A/D
converter, if the resulting output signal from A/D 12 contains six ones, high peak detector 18, which comprises essentially a six input NAND gate and timing circuits, produces a momentary logic 0 pulse such as 28 and otherwise produces a logic 1 level signal. If the signal produced by A/D 12 contains six zeros low peak detector circuit 20, similar to peak detector c rcuit 18 except that it includes a six input NOR gate, which is responsive to six zeros (rather than six ones) produces a momentary logic 0 pulse such as 30 and o-therwise produces a logic 1 level signal.
De-tector circuit 18 is coupled to the count ~A) terminal of a first incrementing counter 40. Counter 40 is connected to a hi~h peak dual threshold detector circuit 42 which has two output terminals labeled HP and HP. Detector 42 operates in accordance with rows 1 and 2 of Table 1 (FIGURE 2) as will be described in more detail later. It essentially comprises a comparator to compare at selected times the count contained in counter 40 with a preselected set of upper and lower nwmbers and further includes logic devices including gates to produce the output signals listed in Table 1. Similarly, detector 20 is coupled to an incremen-ting second counter 46 which is in turn coupled to a low peak detector circwit 48.
Circuit 48, which operates in accordance with rows 3 and 4 73~
~5~ RCA 75,993 of Table 2 (FIGURE 2) is similar in construction to detec-tor 42.
Detector 42 ou-tput HP is coupled to one input of AND gates 50 and 52 while OUtpllt ~IP is coupled to one input of AND ga-tes 54 and 56. ~etector 48, output ~P, is coupled to a second input of AND gates 50 and 56 while output LP is coupled to a second input of AND gates 52 and 54. An update control circuit 60 is coupled to the clock (C) inputs of detectors 42 and 48 and via a short delay D
to the reset (R) inputs of counters 40 and 46 and to a third input of each of AND gates 50, 52, 54 and 56. As will be described hereinafter in more detail, at appropriate points in time circuit 60 procluces a momentary pulse such as 62 to clock the counts in counters 40 and 46 into detectors 42 and 48 respectively and then reset -the counters. At the same time the signals produced by detectors 42 and 48 may be operative -to enable one of ~ND
gates 50, 52, 54 or 56 primed by pulse 62 in accordance with Table 2, FIGURE 3, which will be referred to in more detail later on. AND gates 50 and 54 are coupled -to the Up (UP) and ~own (DN) inputs of an up/down binary third counter 64. AND gates 52 and 56 are coupled to the UP/DN
inputs of an up/down binary fourth counter 66.
Counter 64 is coupled to the control (C) terminal of a binary weigh-ted switched attenuator 68 via a multiconductor cable. System input signal terminal 70, to which is applied an analog signal to be digitized, is coupled to a current buffer 72. The output of current buffer 72 is coupled to the signal input of attenuator 68 of an automatic gain control circuit comprising, in addition to attenuator 68, counter 64 and a fixed gain amplifier 76 to which the outpu-t of attenuator 68 is coupled. Attenuator 68 typically may be a 3:1 attenuator.
As counter 64 is incremented in count by signals through AND ga-te 50, the attenuation in attenuator 68 increases causing the peak-to-peak signal swing through amplifier 76 to decrease thus reducing the gain as measured from the input of a-ttenuator 68 to the output of -6- RCA 75,993 amplifier 76. Conversely, as the count in counter 64 i5 decreased, due to signals from AND gate 54, the attenua-tion of attenuator 68 is decreased causing the peak-to-peak signal swing through amplifier 76 to increase. Counter 64 is typically a si~-bit counter such that attenuator 68 can be set to successive ones of 64 steps of attenuation.
Counter 66 is coupled to a digital--to-voltage converter 78 which is in turn coupled to the ~) terminal of an opera-tional amplifier 80. The (-) terminal is coupled to receive signals from amplifier 76. The output of amplifier 80 is coupled to the input of A/D 12 at terminal 14.
The A/D system of FIGURE 1 is designed to operate with a succession of varying amplitude analog signals of a given fixed duration applied at terminal 70, such as the succession of analog signals representing successive frames o'c information from a television cam~ra.
The input signal, after beiny amplified by amplifier 76 and being offset in amplitude by amplifier 80 in a manner to be described hereinafter, is applied at terminal 14 to A/D converter 12 to be digitized thereby.
The operation of the circuit of FIGURE 1 is a~
follows. It is assumed: (a) that an analog signal is being applied at -terminal 14 which is of the same fixed duration as an inpu-t analog signal being applied at terminal 70; (b) that the signal at -ter~-n~l 14 may be modified in peak-to peak amplitude and in average DC level with respect to the input analog si~nals in a m~n~r to be described. Prior to the application of the analog signal at terml n~l 14, a pulse 62 from circuit 60 clocks the counts in co~nters 40 and 46 into respective detectors 42 and 48 and primes ~ND gates 50, 52, 54 and 56 for reasons to be described hereinafter, then resets counters 40 and 46.
Clock 24 produces pulses at a g:iven fixed rate such as, for example, 4.8 megahertz (MHz). These clock pulses are applied to A/D converter 12 which in response ~'7~
7- RCA 75,993 to each clock pulse, produces a six~bit digi-tal word.
Typically, though not necessarily, portions of the analog signal applied at terminal 14 will be of sufficiently high ampli-tude such -that A/D converter 12 produces some output words of six logic 1 bi-ts. Also typically, though not necessarily, por-tions of the analog signal applied at terminal 14 will be of sufficien-tly low amplitude such that A/D converter 12 produces some output words of si~
logic 0 bits. In the case where the signals applied at terminal 14 relate to signals generated by a TV camera, the six logic l's condition corresponds to very light portions of the scene while the six logic O's condition relates to very dark portions of the scene.
For each output signal of all logic 1 bits from A/D 12, detector 18 produces a logic 0 pulse, such as 28, under timing control of clock 24. For each output signal of all logic 0 bits rom A/D 12, detector 20 produces a lo~ic 0 pulse, such as 30, under kiming control of clock source 24.
Counter 40 counts the number of pulses produced by all logic l's detector 18 while counter 46 counts the number of pulses produced by all logic O's detector 20.
As mentioned previously for a given duration analog signal and fixed rate of clock pulses from clock source 24, the total number of digital words produced by A/D 12 is known in advance. In any application where i-t is desired to use the full dynamic range of the A/D converter 12, a small percentage or fraction of the total number of such digital words should be all logic l's and a small percentage or raction should be all logic O's. If no all l's ancl all O's words occur, the full digital range o~ the A/~
converter is not b~ing utilized. Similarly, if too many all l's and all O's words occur, the A/D converter is being saturated and, in any resulting use of the digi-tal words producecl by A/~ converter 12, may exhibit distortion. For the TV application me~tioned previously, it has been found through experimentation, that the most pleasing picture results when a frame cont~; n;ng between ~~- RCA 75,993 0.5 percent and 1.5 percent all l's and between 1 percent and 2 percent all 0's occurs. Since the numher of words produced by A/D converter 12 for each successive analog signal is known and fixed, the mlmbers which represent the various percentages are also known and are stored in respective detectors 42 and 48 e:ither by hardwiring such as in a counter decoder or in a memory.
By way of example, assume that each analog signal is digitized into 1,000 words by A/D converter 12.
Therefore, detector 42 stores the values 5 and 15 while detector 48 store~ the values 1.0 and 20. After the exemplary analog signal has been applied to term; n~l 14 and digitized and before the nex-t analog signal occurs an initiation pulse, such as 62, occurs which clocks the value in counter 40 into detector 42 and the value in counter 46 into detector 48 while clearing counters 40 and 46.
In detector 42, the number from counter 40 is compared with the numbers representing, fractions 0.5 percent and 1.5 percent. Using the values 5 and 15 and with reference to Table 1, if the count in counter 40 i5 too high, i.e. above 15, terminal HP is set to a logic 1 level and ter~;n~l HP is set to a logic 0 level; if the count is not high enough (i.e. below 5) HP is set to a logic 1 while HP is set to a logic 0 level. Otherwise, both EIP and HP are set to a logic 0 level.
Detector 48 and counter 46 operate in a similar fashion in accordance with rows 3 and 4 of Table 1.
After the above-described operations are performed in detectors 42 and 48, the pulse 62 from circuit 60 primes AND gates 50, 52, 54 and 56. The particular AND gate, if any, which is enabled ~and at most only one AND gate is enabled) is determined in accordance with Table 2. For example, if both HP and LP are logic 1 (Table 2, row 2) gate 50 is enabled which signifies that too much of the~ analog signal is at or above both the upper and lower limits which A/D converter 12 can handle.
In that case, i.n accordance with row 2 o:f Table 2, counter 3,~'~
_g_ RCA 75,993 64 (which initially can be assumed to be set to some arbitrary count between its upper and lower extremes dependent on previous correction conditions) is advanced by one. Thereore, the attenuation in attenuator 68 is increased and the output swing of amplifier 76 is reduced thereby reducing the gain of the a-ttenuator 68-ampllfier 76 combination. Therefore, when the next analog signal is received at terminal 70, the resu].tant signal at terminal 14 is reduced in amplitude from that of the preceding analog signal. There is an assumption that the variation from one analog signal to the next is non-existent or rather small which is generally the case with successive frame signals produced by a TV camera. If gate 54 rather than gate 50 is enabled, (HP = Logic 1, LP = Logic 1) the significance is that the signal at terminal 14 contains no or too few high peak and low peak portions. Therefore, counter 64 is decreased by one, attenuator 68 is attenuated less and the signal swing at the output of amplifier 76 is increased such -that the next analog signal 20. at terminal 70 is amplified by a greater amount than is the preceding signal.
If gate 52 is enabled, the significance is that the DC offset of the analog signal is too high such that more than 1.5 percent of the digital words from A/D 25 converter 12 are all l's while fewer than 1.0 percent of all the words from A/D 12 are all O's. Thereforel counter 66 is incremented by one, so that converter 78 output voltage is lowered and amplifier 80 is changed to provide less DC offset to the following signal applied at terminal 70. Finally, if gate 56 is enabled, the significance is that the DC offset of the analog signal is too low such that fewer than 0.5 percent of the digital words from A/D
converter 12 are all l's while more than 2.0 percent of all words from A/D converter 12 are all O's. Therefore, counter 66 is decremented by one, so that converter 78 output voltage is increased and amplifier 80 is changed to provide more DC offset to the following signal applied to terminal 70.

~lO~ RCA 751993 IE the condition continues for the next analog signal applied at terminal 14 (i.e~, if signal peak-to-peak amplitude is too high or low for too long a duration or if DC offse-t is improper), then the appropriate one of gates 50-56 will again be enabled and one of counters 64 or 66 will be still further incremented or decremented after each successive analog signal applied a-t terminal 70 until conditions are such that no gate is enabled. Both counters 64 and 66 are of the type that will not increment past their upper count or decrement past their lower count. Thus, if signals are outside of the range of that which can be handled by the system, a distorted signal from A/D converter l2 will occur. For the purpose of explaining this invention it is assumed that the nature of the signal applied at terminal 70 and the calibration of the system prevent the distortion condi-tions from occurring.
The no-gate-enabled conditions (rows l, 6, 7, 8 and 9, Table 2) next are considered. Row l shows the situation in which not too many and not too few digital words of all O's and all l1s are produced, so that amplifiers 76 and 80 are adjusted properly (i.e., so that the signal applied at terminal 14 is neither too great nor too small and is not offset in some undesired way. Rows 6, 7, 8 and 9 show the situations in which the signal applied to the A/D converter cause the converter to produce too many and too few all digital l1s words and to produce too many and too few digital all O's words, respectively. In the case of the situation exemplified by row l of Table 2, until the succession of analog signals change in information content to an extent that one or both of amplifiers 76 and 80 need to be readjusted as above-described, neither counter 64 nor 66 will change in value.
In t;he case of the situations represented by rows 6-9 o Table 2, no action occurs. However, (a) when the situation of any one of these lines exists and then the signal fluct-lates to seek new amp].itude or a new ~ RCA 75,993 average level about the DC offset at the output o ampli:Eier ~0 (and thus exhibi-ts one of the conditions exemplified by rows 2~5~ of Table 2, (b) then the converter sys-tem becomes operative, as explained above, to restore the output of A/D converter 12 to one of the conditions described in one of lines 1, 6, 7, 8 and 9 of Table 2.
I-t will be understood that although the A/D
converter system of FIGURE 1 has been designed and described for the situation in which the input analog signal appears in a series of bursts, the system also can operate with a continuous input signal (a~ by supplying to detectors 42 and 48 the actual number of words produced by A/D converter 12 and (b) having the detector adapted to actually compute percentages periodically such as when input pulse 62 occurs.
As another alternative, the numbers preset in detectors 42 and 48 may be chosen to represent allowable limits for a plurality ~for example lOOO) words from A/D
converter 12. Under this set of conditions, a counter (not shown) can be used to coun-t the number of words produced by A/D converter 12 and, when that count is reached, -the counter output can be used to produce initiali~ation pulse 62.

Claims

CLAIMS:

1. A method for assessing one of or both amplitude and average DC level occurring in a given length of time of an analog signal; where the assessment is made in terms of low and high level limits of response range of an analog/digital (A/D) converter to which the analog signal is applied; and where the method includes the step of detecting throughout the given time length the occurrence of digital words of value representing one of the limits of the A/D converter within a series of digital words, which series is produced by the A/D converter throughout the given time length;
wherein the improvement in the detecting step comprises:
detecting within the series of words: (i) an occurrence of a first given number of digital words of first value representing the high limit of the A/D
converter response range and (ii) an occurrence of a second given number of digital words of second value representing the low limit of the A/D converter response range; so that at the end of the given length of time the detected first and second occurrences provide assessment of the analog signal.

2. The method of claim 1, where, in the detecting step the first number of digital words equals or exceeds a first threshold value and the second number of digital words equals or exceeds a second threshold value.

3. The method of claim 1 where, in the detecting step, there is included the step of producing:
(i) one of first and second signals respectively marking the first occurrence and its absence and (ii) one of third and fourth signals respectively marking the second occurrence and its absence.

4. The method of claim 3, wherein the the detecting step comprises (i) making a first count of the number of words of the first value and (ii) making a second count of the number of words of the second value; and the signal producing step comprises: comparing the first and second counts to the first and second thresholds, respectively.

5. The method of claim 1 , where:
the received analog input signal comprises a series of bursts of equal time lengths; and the time length of each burst is equal to the given time length.

6. The method of claim 1 , where:
the received analog input signal is continuous; and the given time length is measured by the length of time required by the A/D converter to produce a given number of words.

7. The method of claim extended to controlling the amplitude of the assessed analog signal, where the assessed analog signal is derived by the step of amplifying a received analog input signal with controllable gain; and including the further step of controlling the gain in the amplifying step in accordance with the values of the digital words;
wherein the step of controlling amplifier gain includes:
(i) decreasing the gain in response to the occurrence of both the first and second given numbers of digital words and (ii) increasing the gain in the absence of both the first and second given numbers of digital words.

8. The method of claim 1 extended to controlling the average DC level of the assessed analog signal, where the assessed signal is derived by the step of controlling a received analog input signal in accordance with the values of the digital words;
wherein:
the step of controlling includes (i) decreasing the average DC level of the amplified analog signal in response to the occurrence of the first given number of digital words and the absence of the second given number of digital words and (ii) increasing the average DC level of the amplified analog signal in response to the occurrence of the second number of digital words and the absence of the first number of digital words.

9. A system for adjusting one of or both the amplitude and the DC level of the received input analog signal with respect to the low and high limits of the input range of the A/D converter in accordance with the method of claim 1 ; wherein the system includes:
first means for amplifying the input analog signal applied thereto and having control terminal means for controlling the analog signal applied to the A/D converter input wherein the A/D converter is responsive to the amplified signal from the first means for producing at an output thereof the series of digital output words whose values are a function of samples of the amplified signal applied to the converter input; and wherein there is included detecting means coupled between the A/D converter output and the control terminal means of the amplifying means;
wherein the improvement comprises:
the detecting means comprising means for making first and second counts of first and second value digital words, respectively, and responsive to both the first and second counts reaching the first and second given numbers respectively, for producing control signals respectively marking the first and second occurrences;
control means coupled between the detecting means and the control terminal means of the amplifying means responsive to the occurrence-marking signals for producing the control signals for application to the control terminal means.

10. The system according to claim 9, wherein:
the detecting means responds to the first and second counts (i) reaching the first and second given numbers, respectively, for producing first and third control signals to mark the first and second occurrences respectively and (ii) not reaching the first and second given numbers, respectively, for producing second and fourth control signals to mark the absence of the first and second occurrences, respectively; and the control means responds to the first through fourth control signals.

11. The system of claim 10 wherein:
the detecting means comprises (i) a high peak detector and companion first incrementing counter (40) and first high peak threshold detector and (ii) a low peak detector and companion second incrementing counter and second low peak threshold detector;
inputs of the high peak detector and low peak detector being coupled to the A/D converter output, each of the high and low peak detectors being operative for applying to an input of a respective one of the first and second counters a signal to increment that counter in response to each digital word of a respective one of the first and second values produced by the A/D converter; and the high-peak and low-peak threshold detectors are operative by comparing the first and second counts in the first and second counters to the first and second given numbers, respectively, for producing the first, second, third, and fourth signals.

12. The system of claim 11, where the amplifying means includes a switched attenuator responsive to digital signals; and wherein the improvement comprises:
the control means comprising first and second gates and a first up-down counter;
the first and second gates being responsive to the first and third signals and to the second and fourth signals respectively, from the high and low peak threshold detectors for producing, when enabled, signals to increment and decrement, respectively, the count in the up-down counter (i) when both peak threshold detectors produce signals marking the first and second occurrences, and (ii) when both peak threshold detectors produce signals marking the absences of the first and second occurrences, respectively, the control means of the switched attenuator is coupled to the output of the up/down counter and is responsive to the count therein for controlling the amplitude of the analog signal applied to the A/D
converter input.

13. The system of claim 10, wherein:
the amplifying means includes further means responsive to a control signal applied to an input thereof for adjusting the DC level of the amplified signal applied to the A/D converter input; and the control means is coupled between the detecting means and the further means input and is responsive to: (i) the first and fourth signals for adjusting toward the low level limit of the A/D converter input the DC level of the amplified signal and (ii) the second and third signals for adjusting toward the high level limit of the A/D converter input the DC level of the amplified signal.

14. The system of claim 13 wherein:
the further means includes an operational amplifier which receives at one input thereof the amplified signal and which produces at an output thereof the amplified signal with its base level controlled in accordance with the level of the signal applied to the other input thereof, for application to the A/D converter input;
the control means comprises third and fourth gates a second up-down counter and a digital-to-voltage converter;
the third and fourth gates being responsive to the first and fourth signals and to the second and third signals respectively, from the high and low peak detectors, for producing signals to increment and decrement, respectively, the count in the second up-down counter;
the output of the second up-down counter is applied to the digital-to-voltage converter to provide at the output thereof voltage at a level in accordance with the count in the second up-down counter; and the output voltage from the digital-to-voltage converter is applied to the other input of the operational amplifier.

15. The system of claim 12 or 14 and further including:
means operative at the end of the given time length for enabling the peak threshold detectors to produce ones of the first, second, third and fourth signals and thereafter operative for enabling the gates and for resetting the first and second incrementing counters.