DE3240175A1 - ADAPTIVE ANALOG / DIGITAL CONVERTER SYSTEM - Google Patents

Description

RCA 75993 / Sch / Ro.
US Ser. No. 316.658
AT: October 30, 1981

RCA Corporation, New York , NY (V.St.A.) Adaptive Analog / Digital Converter System.

The invention relates to the estimation of an analog signal which is sent to the input of an analog / digital converter (A / D converter) in the form of the high and low level limits to which the converter reacts, supplied where the amplitude of the analog signal (measured by the maximum and minimum values of the signal) can change over time. The invention is particularly suitable for a system where the amplitude of the analog signal or the mean value of its maximum and minimum levels · (hereinafter referred to as the mean DC voltage level or simply referred to as DC voltage level) or both with regard to the limits of an A / D converter input are admitted by regulating a controllable amplifier or a DC voltage level regulating circuit (or both), soft a supplied analog input

signal passes through before it reaches the converter.

An A / D converter generates over an observed time Length of an analog signal Digital words whose values represent the amplitudes of samples of the analog input signal represent that were taken over this length of time. Ideally, the ranges of amplitude and change of the mean DC voltage level of an analog signal does not temporally, and the converter is designed so that the sampled amplitudes of the expected analog signal within the upper and lower limits of the converter input range lie (i.e. are coordinated with this) and that, for example, the middle between the upper and lower limit of the range lies at the expected mean DC voltage level of the analog signal. Under these conditions the converter does not need a digital word of a value (for example all zeros or all ones) to represent an analog signal sample that is below or above the limit of the converter input range lies.

A proposal for setting the analog signal amplitude in a non-ideal system for adapting the analog signal to one of the limits of the signal range which the A / D converter responds can be found in US Pat. No. 3,947,806 (inventor: Corkhill et al., issued on March 30, 1976). This patent describes an A / D converter with an automatic gain control circuit, which up or down the amplitude of the analog signal fed to the A / D converter in accordance with the value of the most significant bit of the words generated by the A / D converter. This system admittedly adapts the maximum amplitude of the analog signal to the upper limit of the input range of the converter, however, it is unable to measure the amplitude of the

Increase the analog signal if there are no gaps Maxima in the analog signal amplitude fall below the lower limit of the input range of the converter. Farther the system described in this patent speaks to each digital word of maximum value (which of a Analog signal sample whose amplitude is equal to or greater than the upper limit of the converter input range is) derived, so that the gain control circuit on each individual analog signal sample that is equal to or greater than the upper limit of the input range of the converter. Furthermore are at this system does not take any measures to regulate the mean DC voltage level of the A / D converter supplied Analog signal provided.

In the considerations made here, the values of the digital words generated by an A / D converter can be a minimum (i.e. all zeros) fall or rise to a maximum (all ones) if the middle The amplitude of the analog signal is not adapted to the limits of the input of the A / D converter. The task of Invention consists in a dimensioning of the amplitude of the analog signal with regard to the known lower and lower Upper limits of the signal range to which the A / D converter reacts by measuring the values of the A / D converters generated digital words. Such a dimensioning in turn allows the amplitude to be adjusted or the mean DC voltage level (or both) of the analog signal.

Expressed more formally, the invention relates to a method for measuring the amplitude and / or the base level, which occur in a given length of time of the analog signal, the dimensioning with regard to the lower and upper level limits of the working range

an A / D converter to which the analog signal is fed. As in the prior art, the invention uses The method includes the step of determining the occurrence of a digital word during the given time length, the value of which represents one of the limits of the A / D converter, within a series of digital words, which is generated by the A / D converter during the given length of time.

According to the invention, this includes determining step

(a) the finding within the given length of time both

(i) an occurrence of a first number of digital words within the series that have a first value (for example all ones), which represents the upper limit of the response range of the A / D converter, where the first number is equal to or greater than a first threshold value, and

(ii) the occurrence of a second number of digital words within the series that have a second value have (here all zeros), which represents the lower limit of the response range of the A / D converter, where this second number is equal to or greater than a second threshold value, so that

(b) at the end of the given length of time, the determined first or second occurrence, the desired dimension of the analog signal.

The dimensioning method according to the invention for analog signals can be used in a gain control method to modify the analog signal amplitude or its DC voltage level to set the limits of the Analog signal so that it matches the upper and lower limits of the A / D converter, or for setting the DC voltage level of the analog signal to a desired point within the input range limits of the A / D converter .

Show in the accompanying drawings

Fig »1 shows the electrical block diagram of an analog / Digital converter system according to a preferred embodiment the invention; and

FIGS. 2 and 3 are tables for explaining the mode of operation of some circuit groups of the one shown in FIG A / D converter. "

According to FIG. 1, an input terminal 14 is a An input signal S is supplied to the usual A / D converter circuit 12. For example, the A / D converter 12 can be a Be a 6-bit unit, which is connected to its output terminal 0, which is connected to the system output terminal 16, Provides 6-bit words that have a range of all zeros for an input signal of less than 11 mV too loud ones for an input signal of 700 mV. The A / D converter 12 is multi-core Cables (at least six) with a top-tip detector and an under-peak detector 20 connected. The multi-core The cable is symbolized by a slash 22 crossing the line. With a clock input C each the A / D converter 12, the top-tip detector 18 and A clock source 24 is coupled to the underspeak detector 20.

When each clock pulse occurs, such as a pulse 26, the A / D converter 12 generates a 6-bit word whose value represents the amplitude of the voltage signal fed to input 14. If the resulting output word of the A / D converter 12 contains six ones, in the example of a 6-bit A / D converter, the top-tip detector generates 18, the essentially six input NAND gates and timing circuits, generates a momentary logic 0 pulse such as pulse 28, otherwise it generates

a signal of logic level 1. If that. from the A / D converter If the signal generated contains six zeros, then the lower-peak detector generates 20 ^ - which is similar to the upper-peak detector 18 except that it contains six input NOR gates, and that of six zeros (instead of six Ones) reacts <- a momentary logical O-impulse like the pulse 30, otherwise it generates a signal of logic level 1.

The detector 18 is coupled to the counting input A of a first up counter 40. This counter is with a two-threshold upper-peak detector 42, which has two outputs HP and HP. The detector 42 operates according to lines 1 and 2 of Table 1 (Fig. 2), as will be described in detail later will. It essentially contains a comparison circuit which the count of the counter 40 at selected times with a preselected set of upper and lower numbers, and it still contains logic circuitry with Gate circuits to generate the output signals listed in Table 1. Similarly, the detector 20 is with a coupled to a second up-counter 46, which in turn is coupled to an under-peak detector 48. The latter operates according to lines 3 and 4 of table 2 (FIG. 2) and is constructed similarly to detector 42.

The output HP of the detector 42 is connected to an input of AND gates 50 and 52 connected, while the output HP is connected to an input of AND gates 54 and 56. Of the The output LP of the detector 48 is coupled to a second input of the AND gates 50 and 56, while the output LP ~ is coupled to a second input of AND gates 52 and 54. A state-of-the-art control circuit 60 is connected to the clock inputs C of the detectors 42 and 48 and via a short delay D to the reset inputs R

the counters 40 and 46 and connected to a third input of each of the AND gates 50, 52, 54 and 56. How even closer As will be explained, circuit 60 generates an instantaneous pulse, such as the pulse, at appropriate times 62 to get the counts in counters 40 and 46 in detectors 42 or 48 and then reset the counters. At the same time, those from detectors 42 and 48 signals generated serve to one of the AND gates 50, 52, 54 or 56, which by the pulse 62 accordingly Table 2 in Fig. 3 is prepared to activate how will be explained in detail later. AND gates 50 and 54 are connected to the up and down inputs of a third Binary counter, namely an up / down counter 64 tied together. AND gates 52 and 56 are connected to the up / down inputs of a fourth binary up / down counter 66 connected.

The counter 64 is binary with the control input C. weighted switched attenuator 68 coupled via a multi-core cable. The signal input connector 70 of the system on which an analog signal to be digitized is fed, is coupled to a current buffer 72, the output of which is connected to the signal input of the attenuator 68 of an automatic gain control circuit is performed, which in addition to the attenuator 68 contains a counter 64 and an amplifier 76 of fixed gain, to which the output of the attenuator 68 is coupled

* is. The attenuator 68 is typically a 3: 1 attenuator «

If the count of the counter 64 is incremented by signals passing through the AND gate 50, then the Attenuation of the attenuator 68 is increased, so that the peak amplitude of the amplifier 76 passing through Signal decreases, so the gain between the

Input of attenuator 68 and the output of amplifier 76 is reduced. Conversely, decreases the count value of the counter 64 as a result of signals from the AND gate 54, then the attenuation of the attenuator 68 is decreased so that the peak amplitude of the signal passing through amplifier 76 becomes larger. The counter 64 is typically a 6-bit counter so that the attenuator 68 operates on successive stages of the 64 damping levels can be set.

The counter 66 is coupled to a digital / voltage converter, which in turn is connected to the plus input of a Operational amplifier 80 is coupled, the minus input of which signals from amplifier 76 are fed. The exit of amplifier 80 is coupled to the input of A / D converter 12 at terminal 14.

The analog-to-digital converter system of Figure 1 is designed to be more variable with a sequence of analog signals Amplitude and a given fixed duration, which are supplied at terminal 70, approximately with the sequence of analog signals representing successive frames of information from a television camera. After the input signal has been amplified by amplifier 76 and by amplifier 80 with regard to it If the amplitude has been shifted, as will be described later, it then arrives at connection 14 to the A / D converter 12, from which it is brought into digital form.

The circuit illustrated in Figure 1 operates as follows. Assume that

(A) an analog signal is fed to terminal 14, which is of the same fixed duration as a signal applied to terminal 70, and

(b) that the signal at terminal 14 with regard to its

Peak amplitude and its mean DC voltage level with respect to the analog input signals in one is modified in a manner to be described. Clocks before the analog signal is fed to input 14 a pulse 62 from the control circuit 60 takes the counts of the counters 40 and 46 into respective detectors 42 and and conditions AND gates 50, 52, 54 and 56 for reasons to be described and then sets counters 40 and 46 back.

The clock generator 24 generates pulses of a predetermined fixed frequency, for example 4.8 MHz. These clock pulses are fed to the A / D converter 12, which generates a 6-bit digital word on each clock pulse. Typically, but not necessarily, parts of the analog signal fed to terminal 14 have a sufficiently large amplitude, so that the A / D converter 12 has some output words from 6 bits with the logic value 1 are generated. Likewise, parts of the at the terminal 14 supplied analog signal have a sufficiently small amplitude that the A / D converter 12 some Output words with 6 bits of logic value 0 generated. If the signals fed to terminal 14 are those from a television camera generated signals, then a state with six logical ones gives very bright parts of a Scene again, while a state with six logical zeros corresponds to very dark parts of the scene.

For each output signal of the A / D converter 12 in which all bits represent a logic 1, the detector 18 generates a logic pulse 0, such as the pulse 28, under time control by the clock generator 24. For each output signal of the A / D converter 12 with louder logic zeros, the detector 20 generates a pulse of the logic value 0, such as under the control of the clock generator 24 the pulse 30.

The counter 40 counts the number of pulses received by the Detector 18, which shows the state of all logical ones detects generated pulses, while the counter 46 counts the number of pulses generated by the detector 20 which detects the state of all zeros. For an analog signal of a given duration and fixed clock pulse frequency from clock generator 24 is the total number of digital words generated by A / D converter 12, known in advance. In any application where the full dynamic range of the A / D converter 12 can be used is practically a small percentage or fraction of the total number of these digital words due to louder logical ones and a small percentage or fraction indicated by logical zeros. if if there are no words with all ones or all zeros, then the full digital range of the A / D converter used. On the other hand, if there are too many words with all ones and all zeros, then the A / D converter is overwhelmed, and when the A / D converter 12 generated digital words falsifications occur. In the case of the television applications already mentioned, it has become it has been shown experimentally that the most satisfactory images are obtained when a frame signal is between Contains 0.5 and 1.5% words with all ones and between 1 and 2% with all zeros. Since the number of the A / D converter 12 generated words for each successive analog signal is known and fixed, are the numbers which represent the various percentages are also known and are located in corresponding detectors 42 and 48 either by wiring as in a counter decoder, or held in memory.

For example, assume that each analog signal from A / D converter 12 is digitized into a thousand words

target. Therefore the detector 42 stores the values 5 and 15, while the detector 48 stores the values 10 and 20. After the analog signal used as an example dem Terminal 14 is supplied and digitized and before the next analog signal occurs, an introductory pulse, such as pulse 62, occurs which corresponds to the im Counter 40 keyed in the value contained in the detector 42 and the value contained in the counter 46 in the detector keys and the counters 40 and 46 clears.

In the detector 42, the number is from the counter 40 with the numbers compared, which represent the fractions 0.5% and 1.5%. If at the values 5 and 15 and with reference to Table 1 the count value in the counter 40 is too high, i.e. above 15, then the connection HP is set to the logic level 1 brought and the connection ΪΪΡ to the logic level 0; if the count is not high enough (i.e. below 5), then the output HP is brought to the logic level 1 and the output HP to the logic level 0. Otherwise both outputs HP and HP are brought to logic level 0.

The detector 48 and counter 46 operate in a similar manner according to lines 3 and 4 in Table 1.

After detectors 42 and 48 perform the above-described Have performed operations, the pulse 62 from the control circuit 60 prepares the UND gates 50, 52, 54 and before. The special AND gate, which is activated if necessary (and at most one AND gate is activated) is determined according to Table 2. If, for example, logical ones appear at the outputs HP and LP (Table 2, line 2) then the gate 50 is activated and thus indicates that too much of the analog signal with or is above both the upper and lower limit,

which the A / D converter 12 can process. In this In the event of line 2 of Table 2, the counter 64 (which can be assumed to be initially on any arbitrary count is set between its upper and lower extreme values depending on the previous ones Correction conditions) advanced by one. Therefore, the attenuation of the attenuator 68 is increased, and the output amplitude of amplifier 76 is reduced so that the gain of the combination of the attenuator 68 with the amplifier 76 is reduced. When the next analog signal at terminal 70 arrives, the resulting signal at terminal 14 is therefore in amplitude compared to that of the preceding one Analog signal reduced. It is assumed that from one analog signal to the next none or only a fairly small change occurs, which is generally the case with consecutive frames that generated by a television camera, is the case. If the gate 54 is activated instead of the gate 50 (H? = Logical 1, LP = logical 1), then this means that the signal at connection 14 contains no or too few upper and lower peak components. Hence the counter reset by one, the attenuator 68 attenuates less, and the signal amplitude at the output of the amplifier 76 is enlarged so that the next analog signal at terminal 70 is more than the previous signal is reinforced.

If gate 52 is activated, it means that the DC offset of the analog signal is too high, so that more than 1.5% of the digital words from the A / D converter have all ones, while less than 1.0% of all Words from the A / D converter have 12 zeros. Therefore the count of the counter 66 is increased by one, so that the output voltage of the converter 78 becomes lower

and the amplifier 80 is set so that the next at the terminal 70 supplied signal receives a lower DC voltage shift. An activation of the gate Finally, 56 means that the DC offset of the analog signal is too low, so that less than 0.5% of the digital words from the A / D converter 12 are all ones while more than 2% of all words from the A / D converter have 12 all zeros. Hence the count in the counter 66 is reduced by one, so that the output voltage of the Converter 78 is increased and the amplifier 80 is set so that the next, at terminal 70 supplied Signal receives a stronger DC voltage shift.

If the state for the next supplied to terminal 14 Analog signal continues (i.e. if the peak amplitude of the signal is too high or too low for too long or if the DC offset is incorrect) then the appropriate port will be gates 50-56 activated again, and one of the counters 64 or 66 increases or decreases its count value again after each successively applied analog signal at terminal 70 until the conditions are such that no gate is activated. Both counters 64 and 66 are such that they do not increment above their high count or below theirs Do not decrease the lower count. So if the signals are outside the range processed by the system can be, then the A / D converter 12 delivers a corrupted signal. For the purpose of explaining the Invention it is assumed that by the nature of the signals applied to terminal 70 and by the calibration the system prevents corruption states appear.

Next, consider the states where there is no gate is activated (lines 1, 6, 7, 8 and 9 in Table 2).

Line 1 shows the case in which not too many and not too few digital words with all zeros or louder Ones are generated so that amplifiers 76 and 76 are properly set (i.e. so that that at terminal 14 is neither too large nor too small and is also not shifted in an undesirable manner). Lines 6, 7, 8 and 9 show cases where this The signal fed to the A / D converter too many or too few words with all digital ones or too many or generate too few words with lots of digital zeros. In the case of line 1 of table 2 changes neither the counter 64 nor the counter 66 its value until the successive analog signals their information content to the extent that one or both amplifiers 76 and 80 are adjusted in the manner described above need to be changed.

In the cases shown in lines 6 to 9 of Table 2, nothing happens. However, if (a) a state in one of these lines prevails and then the signal changes to a new amplitude or a new mean level to set the DC voltage shift at the output of amplifier 80 (and this represents one of the states in rows 2 to 5 of Table 2), (b) then the converter system begins to operate in the manner described above and brings the output of the A / D converter 12 to one of the states as shown in one of the rows 1, 6, 7, 8 and 9 of the table are described.

If the analog / digital converter system of FIG. 1 is also described for the case that the analog input signal occurs as a series of bursts, it can also work with a continuous input signal, by (a) the detectors 42 and 48 the actual

Number of words generated by the A / D converter 12 are supplied and (b) the detector is so adapted is that it actually periodically calculates percentages, such as when the input pulse 62 occurs.

As a further alternative, those in the detectors can be used 42 and 48 preset numbers are chosen so that they are acceptable limits for a plurality of words (e.g. 1000) from A / D converter 12. A counter (not shown) can be used for these states can be used to count the number of words generated by the A / D converter 12, and if this count is reached, the counter output signal can be used to generate of the introductory pulse 62 can be used.

Claims (15)

RCA 75993 / Sch / Ro. US Ser. No. 316,658 AT: October 30, 1981 TELEPHONE 089/4 70 60 06 TELEX 522 638 TELEGRAM SOMBEZ RCA Corporation, New York, N.Y. (V.St.A.) Adaptive analog / digital converter system. Claims 1.) Procedure for dimensioning the amplitude and / or the mean DC voltage levels which occur in a given length of time of an analog signal, the Dimensioning with regard to the upper and lower level limits of the processing range of an analog / digital converter (12) takes place, to which the analog signal is fed, with a method step of determining the occurrence of digital words, during the given length of time, the value of which is one of the limits of the analog / digital converter represent, within a series of digital words borrowed from the analog-to-digital converter during the given time Length are generated, characterized in that in the determining step within half of the series of words is found (i) an occurrence of a first given number of digital words of a first value (all ones) which contain the Upper limit of the working range of the analog / digital converter represent, and (ii) an occurrence of a second predetermined number of digital words of a second value (all zeros), which the lower limit of the working range of the analog / digital converter represent in such a way that at the end of the given length of time the first and second occurrences are determined for measurement of the analog signal. 2.) The method according to claim 1, characterized in g e, that in the determining step the first number of digital words is equal to or greater than a first threshold value and the second number of digital words equal to or greater than a second Threshold is. 3.) The method according to claim 1 or 2, characterized in that in the determining step
(i) a first or second signal (HP, HP) is generated, which respectively mark the first occurrence or its absence and (ii) a third and a fourth signal (LP, LP) are generated, each of which is the second occurrence or Mark missing. 4.) The method according to claim 3, characterized in that in the determining step
(i) a first count of a number of words of the first value and (ii) a, second count of the number of words of the second value is carried out and that when the signal is generated, the first and second count values are compared with a first and second threshold value, respectively will. 5.) The method according to any one of claims 1 to 4, characterized in that the supplied analog input signal has a series of bursts of equal temporal lengths and that the temporal Length of each burst is equal to the given length of time. 6.) The method according to any one of claims 1 to 4, d a characterized in that the supplied analog input signal is continuous and that the predetermined length of time by the length of time is measured, which the analog / digital converter needs to generate a predetermined number of words. 7.) The method according to any one of claims 1 to 6, characterized in that the amplitude of the analog signal to be measured is additionally regulated, the measured analog signal being derived by amplifying a supplied analog input signal (from 70), with a corresponding to the values of the digital words adjustable gain, and that in the gain control
(i) the gain is decreased upon occurrence of both the first and second predetermined numbers of digital words, and (ii) the reinforcement in the absence of both the first and second predetermined number of digital words is increased. 8.) The method according to any one of claims 1 to 7, characterized in that it is used for Regulation of the mean DC voltage level of the metered analog signal is extended to the metered signal derived by regulating an applied analog input signal (from 70) according to the values of the digital words will that with the scheme (i) the mean DC voltage level of the amplified analog signal as a function of the occurrence of the first given number of digital words and the lack of the second given number of digital words will and (ii) that the mean DC voltage level of the amplified analog signal as a function of the occurrence of the second Number of digital words and the lack of the first number of digital words is increased. 9.) System for setting the amplitude and / or the DC voltage level of a (at 70) supplied analog Input signal with regard to the upper and lower limits of the input range of the analog / digital converter (12) according to the method of claim 7 or 8, wherein one first device (72, 68, 76, 80) is provided for amplifying the supplied analog input signal, which a control input (C of 68 or + of 80) for controlling the input (14) of the analog / digital converter supplied has analog input signal, in which, furthermore, the analog / digital converter when the amplified Signal from the first device at its output (16) provides a series of digital output words whose Values depend on the sample values of the amplified signal fed to the converter input, and in the case of which a Detector (18, 40, 42; 20, 46, 42; 50-56, 64, 66) between the output of the analog / digital converter and the control input of the amplifier is switched, thereby characterized in that the detector has a first Means (18, 40, 42; 20, 46, 48) having a first and a second count of digital words of a established first and second values and responding to the fact that the first and second counts the first and second, respectively predetermined number reached, for generating output signals (HP, LP), which mark the first or second occurrence, and that a control circuit (50-56, 64, 66, 78) is provided, which is inserted between the detector and the control input of the amplifier and on the signals marking the occurrence generate the control signals for supply to the control connection. 10.) System according to claim 9, characterized in that that the detector when the first and second count (i) reaches the first or second predetermined number, a first and a third control signal (HP, LP) for marking the first or »second occurrence are generated and (ii) the first or second predetermined number is not reached, a second and fourth control signal (HP, LP) to mark the absence of the first or second occurrence generated, and that the control circuit is responsive to the first through fourth control signals. 11.) System according to claim 10, characterized that the detector (i) a top-tip detector (18) and an associated one first up counter (40) and a first upper-peak threshold value detector (82) and (ii) an under-peak detector (20) with associated second up counter (46) and a second underspeak threshold detector (48) has that the inputs (22) of the top-tip detector and the Under-peak detector with the output of the analog / digital converter are coupled and the top-tip detector and the under-peak detector has an input A each supply a signal to one of the first or second counters to increment the count of that counter, each time when the analog-to-digital converter generates a digital word of a corresponding one of the two (first and second) values , and that the upper-peak threshold value detector and the lower-peak threshold value detector (42, 48) the first and Compare the second count value in the first or second counter (40, 46) with the first or second predetermined number and generate the first, second, third and fourth signals (HP, HP, LP, LP). 12.) The system of claim 11, wherein the amplifier contains a switched attenuator (68) responsive to digital signals, thereby geken that the control circuit has a first and a second port (50, 54) and a first up counter (64) contains that the first and the second port upon application of the first and third signals (HP, LP) and des second and fourth signals (HP, LP) from the upper-peak and lower-peak detectors when activated Provide increase or decrease of the count value in the up / down counter if (i) both peak threshold detectors generate signals (HP and LP) which mark the first and second occurrences and (ii) both peak threshold detectors generate signals (HP, LP) indicating the absence of the first and second occurrence, respectively to mark, and that the control input (C) of the switched attenuator (68) with the output of the up / down counter is coupled and on its count value the amplitude of the input of the analog / digital converter fed Analog signal regulates. 13.) System according to one of claims 10, 11 and 12, characterized in that the Amplifier contains a further device (80) which, when the control signal is fed to an input (+) DC voltage level of the input of the analog / digital converter supplied amplified signal adjusts, and that the control circuit (52, 56, 66, 78) between the Detector and the input of the further device is switched and (i) when the first and fourth signals are supplied, the DC voltage level of the amplified signal is set in the direction of the lower level limit at the input of the analog / digital converter and
(ii) when the second and third signals are supplied, the DC voltage level of the amplified signal is set in the direction of the upper level limit at the input of the analog / digital converter. 14.) System according to claim 13, characterized in that that the further device has an operational amplifier (80) at one input (-) the amplified signal is fed in and the amplified signal at its output with corresponding to the level of the signal fed to its other input (f ·) Basic level for supply to the analog / digital converter produces that the control circuit a third and a fourth port 52,56), a second up / down counter (66) and a digital / voltage converter (78) contains that the third and fourth port when the first and fourth signals (HP, LP) and the second are supplied, respectively and third signals (HP, LP) from the top and bottom Under-peak detector signals to increase or decrease of the count value is generated in the second up / down counter, the output signal of which is sent to the digital / voltage converter is supplied, which at its output generates a voltage having a level corresponding to the count value | in the second up / down counter, and that the The output voltage of the digital / voltage converter is fed to the other input (+) of the operational amplifier will. 15.) System according to claim 12 or 14, characterized characterized in that a device (6O, D) at the end of the predetermined length of time, the peak threshold value detectors for generating the first, second, third or fourth signal activated and then activated the gates and the first and second up counters resets.