JPS58150198A - メモリのチエツク方式 - Google Patents

メモリのチエツク方式

Info

Publication number
JPS58150198A
JPS58150198A JP57033550A JP3355082A JPS58150198A JP S58150198 A JPS58150198 A JP S58150198A JP 57033550 A JP57033550 A JP 57033550A JP 3355082 A JP3355082 A JP 3355082A JP S58150198 A JPS58150198 A JP S58150198A
Authority
JP
Japan
Prior art keywords
memory
data
group
gates
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57033550A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0219496B2 (enrdf_load_html_response
Inventor
Masaru Wakabayashi
勝 若林
Masahiro Teranishi
寺西　正弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Usac Electronic Ind Co Ltd
Original Assignee
Usac Electronic Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Usac Electronic Ind Co Ltd filed Critical Usac Electronic Ind Co Ltd
Priority to JP57033550A priority Critical patent/JPS58150198A/ja
Publication of JPS58150198A publication Critical patent/JPS58150198A/ja
Publication of JPH0219496B2 publication Critical patent/JPH0219496B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
JP57033550A 1982-03-03 1982-03-03 メモリのチエツク方式 Granted JPS58150198A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57033550A JPS58150198A (ja) 1982-03-03 1982-03-03 メモリのチエツク方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57033550A JPS58150198A (ja) 1982-03-03 1982-03-03 メモリのチエツク方式

Publications (2)

Publication Number Publication Date
JPS58150198A true JPS58150198A (ja) 1983-09-06
JPH0219496B2 JPH0219496B2 (enrdf_load_html_response) 1990-05-02

Family

ID=12389658

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57033550A Granted JPS58150198A (ja) 1982-03-03 1982-03-03 メモリのチエツク方式

Country Status (1)

Country Link
JP (1) JPS58150198A (enrdf_load_html_response)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0189615A3 (en) * 1985-01-28 1988-07-27 Koninklijke Philips Electronics N.V. Method of using complementary logic gates to test for faults in electronic compounds
JPS63201858A (ja) * 1987-02-18 1988-08-19 Nec Corp メモリ試験方式

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147924A (en) * 1975-06-13 1976-12-18 Fujitsu Ltd Memory unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147924A (en) * 1975-06-13 1976-12-18 Fujitsu Ltd Memory unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0189615A3 (en) * 1985-01-28 1988-07-27 Koninklijke Philips Electronics N.V. Method of using complementary logic gates to test for faults in electronic compounds
JPS63201858A (ja) * 1987-02-18 1988-08-19 Nec Corp メモリ試験方式

Also Published As

Publication number Publication date
JPH0219496B2 (enrdf_load_html_response) 1990-05-02

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