JPS58149531A - Controlling method of bus use right - Google Patents

Abstract

PURPOSE:To perform the maintenance in each device without having influence upon operations of other devices, by providing one bus use request signal line connected in common to plural devices having a common bus and assigning priority levels to respective devices. CONSTITUTION:When a bus use request is generated in a bus access circuit BAS, a signal REQi is activated. At this time, if a signal line L is in an inactive state, the signal REQi passes through a gate NAND and sets an FF 1. If the signal line L is in an active state, the gate NAND is closed, and the FF 1 is not set. When the FF 1 is set, the output of the FF 1 activates the signal line L through an inverter INV1, and a signal DATAi is outputted to activate a signal line (i) assigned to a device A out of signal lines constituting a bus B. If the contention is caused by request signals from other devices, a priority level discriminating circuit PRIC makes a signal PRI high-level and outputs a bus activation confirming signal ACKi through an FF 2 after a prescribed time only when the device A among devices corresponding to activated signal lines has the highest priority level.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bus usage right control method in a common bus system configured such that a parallel bus is commonly used by a plurality of devices.

In a common bus system, there may be competing requests for bus use from multiple devices. Therefore, as a method to resolve such conflicts, a management device having a conflict management function is provided, and other devices send a bus usage right request signal to this management device and receive a confirmation signal sent from the management device. Centralized management is carried out to obtain the right to use the bus.

However, such conventional methods require that the management device be running on the bus.

Therefore, if the management device is suspended for maintenance or the like, all devices using the bus must also be suspended.

In order to solve these conventional drawbacks, the present invention provides a single bus use request signal line so as to commonly connect a plurality of devices that commonly use the bus, and also provides a bus use request signal line that is predetermined for each device. One of the signal lines constituting the bus is assigned according to the priority order, and the right to use the bus can be controlled according to the priority order based on the transmission and reception of signals between each signal line and each device. It is.

Hereinafter, a detailed explanation will be given using the drawings.

FIG. 1 is a circuit diagram showing an example of a circuit used in the present invention, in which L is a signal line through which a bus use request signal (hereinafter referred to as a request signal) is transmitted, and B is a parallel bus through which data and addresses are transmitted. (hereinafter referred to as bust), NAND is a Nant gate, ANDU ant game), FFI, FF2 is a D-type flip 7o block, INVI, INV2 is an inverter, DI, D2 is a delay circuit, pRIC is a priority determination circuit, BAS is a bus access In the circuit, T1 to T3 are terminals.

One input terminal of NAND is a signal RE related to the presence or absence of a bus use request of the bus access circuit RAS.
Qi is connected to the output terminal T1, the other input terminal is connected to the signal line and the output terminal of the inverter Nv1,
The output terminal is connected to the S terminal of the flip-flop FFI. Note that an open collector output inverter is used as the inverter INVI. The Q terminal of the flip-flop FFI is connected to the input terminal of the inverter INVIO and one input terminal of the AND, and is connected to the flip-flops FFI and FF2 via the delay circuit D1.
The D terminal is connected to each T terminal of the flip-flop FF.
The R terminal is connected to the output terminal T2 of the reset signal RESETi of the bus access circuit RAS.

The S terminal of the flip-flop FF2 is connected to a common potential point, the Q terminal is connected to the input terminal of the delay circuit D20, and the R terminal is connected to the reset signal RESET of the bus access circuit RAS.
It is connected to output terminal T2 of i. The output terminal of the delay circuit D2 is connected to the output terminal via the inverter INV2.
It is connected to the other input terminal of ND and also to the input terminal T3 of the bus access circuit's confirmation signal ACKi. An output terminal of the AND is connected to a predetermined signal line 1 constituting a bus B assigned according to a predetermined priority order. All signal lines constituting the bus B are connected to the priority determination circuit PR:IC.

In such a configuration, when a bus use request is generated in the bus access circuit (3) BAS, the signal REQi is activated (high level). In this state, if no other device is using bus B, that is, if the signal line is in an inactive state (signal REQ is at H level), then signal RE
Qi passes through the NAND gate and sets the flip-flop FFI. Note that if the signal line is in the active state (signal REQ is at L level), the NAND game)
NAND is closed and flip-flop F remains closed until another device finishes using bus B and sets signal REQ to H level.
FI cannot be set. 7 lip flop F
When FI is set, an L-level signal REQ that activates the signal line is sent to the signal line through the inverter INVI. An H level signal DATAi for activating signal line 1 is sent to signal line 1 of .

By the way, since multiple devices (for example, B and C) are connected to the signal @L and bus B in addition to device A,
During the delay time τ from confirming that the signal line is inactive (4) and activating the signal line, an L-level signal REQ is sent from multiple devices to activate the signal line. may be sent, resulting in a race condition. Such a race condition can be resolved by the following operations.

That is, the priority determination circuit PRIC reads the status of the signal lines that make up the bus B, and outputs the output signal PRI only when it determines that its priority is the highest among the activated signal lines. Activate it to H level. This output signal PRI is taken into each T terminal of the flip-flops FFI and 'FF2 after a certain period of time D1 has elapsed since the signal REQ was activated. Here, the time D1 is set by the delay circuit D1, and is sufficient time for the signals from each competing device to arrive at each unique signal line of the bus B, that is, the delay time described above. υ is also set for a long time. As a result, signal PRI is activated in only one device, and only that device has flip-flop FF2.
is set, flip 70 knobs FFI of other equipment.

Both FF2 are reset. When the flip-flop FF2 is set in this way, after a sufficient time D2 required for other devices to read its own signal PRI, the internal signal line 1 that constitutes the bus B is closed by closing the AND. inactivate. At the same time, an activated confirmation signal ACK1 is sent to the output terminal T3,
Notify the bus access circuit RAS that the right to use the bus has been obtained. As a result, the bus access circuit RAS accesses the bus B and executes predetermined processing. And bus B
When the access is completed, the activated reset signal RESETi is sent from the bus access circuit RAS to the R terminals of the flip-flops FFI and FF2, and the reset signal RESETi is sent to the R terminals of the flip-flops FFI and FF2.

FF2 is reset.

FIG. 2 is a timing diagram for explaining such a conflict resolution operation, and illustrates the relationship between three devices A to C. In Figure 2, (a) to (,) are priority 1
(f) to (
h) represents the signals of each part related to the device B having the second priority, and (1) to (k) represent the signals of each part related to the device C having the third priority.

At time t, the signal REQj of device B is activated, and the signal DATAj and signal PRIj are also activated, and at time t2 from time t□ to time t4, which has elapsed in time.
, the signal REQk of the device C is activated and the signal DAT
Ak is also activated. Here, since the priority of the device is the highest, when each signal of device A is activated at time t2, the signal PRIj of device B is deactivated.

At time t5, when a certain period of time Dlj has elapsed from time t1, device B reads the state of signal PRIj and outputs signal REQj.
and inactivate DATAj. At time t6, when a certain period of time Dli has elapsed from time t2, device A outputs signal PR.
The state of Ii is read, and the active state of signals DATA1 and PRIi is maintained until time t8 at which a predetermined period of time D21 has elapsed. Note that the signal REQi remains active until it is reset at time tq. At time t7, when a certain period of time Dlk has elapsed from time t3, device C reads the state of signal PRIk and outputs signals REQk and DAT.
Inactivates Ak. Device A activates the confirmation signal ACKi (7) at the aforementioned time t8, activates the reset signal RESET1 at time t9 when the bus use is finished, and outputs the signal R.
EQi and confirmation signal ACKi are inactivated.

As described above, according to the present invention, since each device itself generates the confirmation signal to the bus access circuit, there is no inconvenience associated with centralized management by a conventional management device, and the confirmation signal to the bus access circuit is generated for each device. Maintenance can be performed without affecting the operation of other devices. Furthermore, although a priority order is determined for each device, the right to use the bus is not acquired based on the priority order, except when a device with a lower priority has to wait when there is a conflict of requests to use the bus. There is no difference in the time required. Furthermore, only one signal line needs to be added, and the configuration can be relatively simple.

Note that the bus used in the present invention may be a data bus or an address bus.

As explained above, according to the present invention, a method (8) for controlling bus usage rights in a common bus system that is excellent in maintainability and can increase the operating rate of the system can be realized, and the practical effects are great.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an example of the circuit used in the present invention, Figure 2 is a circuit diagram showing an example of the circuit used in the present invention.
The figure is a timing diagram for explaining the present invention in detail. L...bus use request signal line, B...bus, NAND
... Nantes Gate, AND... And Gate, FF
1. FF2...D type flip-flop, INVI,
INV2...Inverter, Dl, D2...Delay circuit, PRIC...Priority determination circuit, RAS...
Bus access circuit, T1-T3,,,terminals.

Claims (1)

[Claims] In a common bus system configured so that a parallel bus is commonly used by multiple devices, one bus use request signal line is provided to commonly connect each device, and a predetermined priority signal line is provided for each device. One of the signal lines that make up the bus is assigned according to the order, and after confirming that the bus use request signal line is inactive, the bus use request signal line is activated, and then the other signal lines that request bus use are assigned. Indicates to the device that the bus is in use, activates the signal lines that make up the assigned bus, and then reads the status of all signal lines on the bus after a certain period of time and determines that the priority is the highest. A bus usage right control method characterized in that the bus usage right is obtained only for