JPH04332066A - Resource acquiring method for multiprocessor system - Google Patents

Abstract

PURPOSE:To easily manage resources by adding a request signal receiving logical circuit to a device to be shared by plural processor systems and allowing a slave processor to acquire device using right without being managed by the master processor system. CONSTITUTION:The processor systems 1 to 4 use devices 5, 6 through a system bus 7. The request signal reception controlling logical circuit consisting of an I/O buffer 10, a register 11, etc., is arranged on a connecting position between the devices 5, 6 and the bus 7. When the system 2 uses the device 5 e.g. a device request signal is sent. When the device 5 clears a register 11 when the device 5 itself is not used. When the device request signal is written in the register 11, the register 11 is turned to a write inhibited state. The system 2 reads out the output of the register 11 through the I/O buffer 10, compares the read output with the device request signal, and when both the signals coincide with each other, the reception of the request is judged and operation is commanded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resource acquisition method for a multiprocessor system when each processor system in the multiprocessor system shares a device connected to a system bus.

0002

2. Description of the Related Art Conventionally, in a resource acquisition method for this type of multiprocessor system, one processor system is used as a master to manage all resources, and processor systems other than the master operate as slaves, and each slave processor Each time the system uses a device, it requests the master processor system to acquire the right to use the device through inter-processor communication, and starts operating the device after receiving permission to use the device from the master processor system.

0003

[Problems to be Solved by the Invention] In the conventional resource acquisition method of the multiprocessor system described above, the master processor system is required to manage all resources.
This method has drawbacks such as complicated control and increased processing load.

0004

Means for Solving the Problems The system of the present invention provides at least one system bus connected to a system bus connecting a plurality of processor systems so as to be accessible from the processor system.
Each device has a byte register that can be read and written from and written to by each processor system, and if the output value of all bits of this byte register is zero, writing to this register is permitted, and writing is prohibited in other cases. A request signal reception circuit having a logic circuit is provided.
Each said processor system, when using said apparatus,
After creating a device use request signal allocated in bits for each processor system in advance and transmitting it to the byte register, the contents of the byte register are read, and only when this contents match the contents transmitted by the device itself, the device is activated. Access is made assuming that the usage right has been acquired, and the operating procedure is set such that the device clears the byte register when the operation requested by the processor system is completed.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a block diagram of one embodiment of the present invention. Reference numeral 1 indicates a master processor system, 2 to 4 are slave processor systems, 5 and 6 are devices shared by each of the processor systems 1 to 4, and 7 is a system bus. Master processor system 1 instructs slave processor systems 2 to 4 via system bus 7 to use device 5 or 6 to perform a predetermined operation. In the process of performing operations specified by the master processor system 1, the slave processor systems 2 to 4
When necessary, a device use right request signal is sent to the device 5 or 6 via the system bus 7, and after confirming that the request has been accepted, data instructing the operation is sent to the device 5 or 6. Send. The device use request signal is 1
This is byte data, and the bits are assigned in advance to indicate the number of the requesting slave processor system. For example, the 2nd to 4th bits are assigned to slave processor system numbers 2 to 4, respectively. If there is a request, only the relevant bit is set to '1'. Note that the slave processor systems 2 to 4 operate asynchronously and issue requests to the device 5 or 6 at any time.

FIG. 2 shows an example of the structure of the request signal reception control logic circuits inserted and connected to the connection points of the devices 5 and 6 with the system bus 7 of this embodiment. For example, when the slave processor system 2 uses the device 5, a device use request signal is created and sent to the control logic circuit of the device 5 via the system bus 7. In the device 5, the register 11 is cleared when the device is not used, and the output values of the output terminals Q0 to Q7 are all '0'. In this case, the output terminals Q0 to Q of register 11
The output value of the OR circuit 12 whose input terminal is connected to 7 is '0'.
'become. The output signal of the OR circuit 12 is input to the inhibit input terminal of the inhibit circuit 13, and the write signal applied to the other input terminal of the inhibit circuit 13 passes through and is added to the register 11 without being output inhibited. When the device use request signal from the slave processor system 2 is written, the output data of the register 11 becomes {00100000}. The slave processor system 2 reads the output content of this register 11 via the system bus 7, compares it with the device usage right request signal created by its own system, and if it is the same, determines that the request has been accepted, and then Sends data instructing the device 5 to operate. Until the operation requested by slave processor system 2 is completed,
When a request is made to the device 5 from another slave processor system, that slave processor system sends a device usage right request signal to the device 5. At this time, the output of the register 11 is as shown above. Since the output value of circuit 12 is '1', prohibition circuit 1
3 prohibits the application of a write signal to the register 11, and the device use right request signal sent from the slave processor system is not written to the register 11. The slave processor system that issued the request reads the contents of register 11 and compares it with the device usage right request signal sent from its own system, but the content read at this time is the device usage right request signal written by slave processor system 2. Since there is a match, it is determined that the request was not accepted. When the device 5 completes the operation requested by the slave processor system 2, it notifies the slave processor system 2 of the completion of the operation and also provides a reset signal to the register 11 to clear the written contents.

[0008]

As explained above, according to the present invention, by adding a logic circuit for receiving request signals to a device shared by a plurality of processor systems, slave processors can be operated without being controlled by a master processor system. It is possible to acquire the right to use the device, facilitate resource management in the master processor system, and reduce the processing load.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the invention.

FIG. 2 is a circuit diagram of a request signal reception circuit added to devices 5 and 6 in FIG. 1;

[Explanation of symbols]

1 Master processor system 2 to 4 Slave processor system 5, 6
Device 7 System bus 10 Input/output buffer 11 Register 12 OR circuit 13 Inhibition circuit

Claims (2)

[Claims] 1. At least one device connected to a system bus connecting a plurality of processor systems so as to be accessible from the processor system, each of which has a byte register that can be read and written by each processor system, and a byte register that can be read and written from each processor system, and a byte register that can be read and written from each processor system, and a byte register that can be read and written from each processor system. A request signal reception circuit is provided with a logic circuit that permits writing to this register when the output value of the bit is zero, and prohibits writing in other cases, and each of the processor systems uses the device. When doing so, create a device use request signal allocated in bits for each processor system in advance, send it to the byte register, read the contents of the byte register, and when the contents match the transmitted contents, Assuming that you have acquired the right to use this device,
A resource acquisition method for a multiprocessor system, characterized in that an operation procedure is set such that the byte register is cleared when the device accesses the byte register and completes the operation requested by the processor system. 2. The logic circuit includes an OR circuit that outputs a logical sum signal of each output bit of the byte register, and an output signal of the OR circuit applied to an inhibit input terminal, and an OR circuit that outputs a logical sum signal of each output bit of the byte register, and an output signal of the OR circuit that is applied to an inhibit input terminal. 2. The multiprocessor system according to claim 1, further comprising: a prohibition circuit which applies a write instruction signal to the other input terminal of the byte register and supplies an output signal to the write instruction input terminal of the byte register. method.