JPS58149525A - Automatic power supply controller - Google Patents

Abstract

PURPOSE:To reduce the number of microprocessors, by switching and using programs, which control microprocessors, before and after the power supply to an information processing device in case of the automatic power supply control. CONSTITUTION:When an information processing device 1 is used, a microprocessor 3 takes partial charge of processings required for the information processing device 1 in accordance with a program stored in a storage part 7 and is operated as a private processor for these processings to improve the price/performance ratio of the information processing device. When the information processing device 1 is not used, the microprocessor 3 performs the automatic power supply processing in accordance with a program stored in a storage part 5 to contribute to reduction of the labor. Consequently, not only the automatic power supply processing but also other required processings after power supply are performed in one microprocessor.

Description

[Detailed description of the invention] The present invention relates to an automatic power supply control device for an information processing device.

In recent years, as part of efforts to save labor in information processing devices, the problem of automatic power-on and power-off has been attracting attention.

When automatically powering on and off an information processing device, it is important not only to turn on and off the AC power at a predetermined time, but also to check and maintain the environmental conditions and wait for the DC power voltage generated from the AC power supply to stabilize. In addition, during these controls, the control sequence is advanced while checking the response signal to the control signal, improving reliability and further strengthening the abnormality display function. This has led to the emergence of automatic power supply control devices equipped with microprocessors and capable of meeting the above-mentioned functional enhancements through program control. Such an automatic power supply control device is generally operated by a power source independent of power on/off of the information processing device to be controlled.

The microprocessor installed in the automatic power control device of such conventional information processing equipment is used only at the time when the power is turned on and off, and after the power is turned off and before it is turned on.
There is a disadvantage that the information processing apparatus is hardly used and remains idle during the time when the power is turned on.

An object of the present invention is to provide an automatic power control device for an information processing device that eliminates the drawbacks of the conventional device described above, makes more efficient use of the installed microprocessor, and reduces the number of microprocessors in the information processing system. It's about doing.

The apparatus of the present invention includes a first storage means for storing an automatic power-on processing program and a status determination program for an information processing device, and a first storage means for storing a predetermined processing program including an automatic power-off processing program for the information processing device. 2
storage means, signal holding means for holding the status signal of fang 1 or fang 2 in response to a microprocessor reset signal, and accessing the status determination program by restoring to the initial state in response to the microprocessor reset signal. reads the status signal held in the signal holding means, and when the status signal is the first status signal, operates according to the processing program stored in the second storage means to output the second status signal. In some cases, the information processing device is powered on in response to a microprocessor operated by an automatic power-on processing program stored in the first storage means and a power-on signal supplied from the microprocessor. Said first
generates a second status signal and the microprocessor reset signal, turns off the power to the information processing device in response to a power cutoff signal supplied from the microprocessor, and generates a second status signal and the microprocessor reset signal. and power control status signal generation means.

Next, the present invention will be explained in detail with reference to the drawings.

The figure is a block diagram of one embodiment of the present invention.

One embodiment of the present invention includes an information processing device 1 and a power supply control device 2. In addition to the storage unit 7 (second storage means) and power supply unit 8 shown here, the information processing device 1 also includes a main memory, various processing units, an input/output unit, a control unit, etc. for power control. This includes equipment that is largely unrelated and essential for information processing, but is omitted from the diagram. The power supply control device 2 includes a microprocessor 31. A power supply control section 4 (source control status signal generation means), a storage section 5 (storage means for fl).

It includes a register 6 (signal holding means) and a clock section 9.

The power supply to the information processing device 1 is controlled by the power supply control device 2, and the power supply control device t2 is constantly supplied with power, but the information processing device 1 is supplied with power only when in use.

The storage unit 5 is a program for automatic power-on.

Storage unit 7tj: stores programs for predetermined processing (including automatic power-off processing) necessary for the information processing device 1; The status determination program is a program that determines whether the information processing device 1 is powered on or not, and designates a program to be used by the microprocessor 3, which will be described later.

The microprocessor 3 is connected to the connection line 14? The microprocessor reset signal supplied via the microprocessor reset signal restores the initial state, accesses the status determination program stored in the storage section 5, and reads the value of the register 6 based on this program. When the value of register 6 is logic If □ It (second status signal), the automatic power-on program stored in storage unit 5 is accessed, the processing necessary for automatic power-on is performed according to this program, and the value of register 6 is Value is logical 111+
1 (first status signal), a program stored in the storage unit 7 is accessed and predetermined processing necessary for the information processing device 1 is assigned to the program according to this program.

When a status signal supplied from the power supply control section 4 with six registers is received via the connection line 15, and a microprocessor reset signal is also supplied from the power supply control section 4 via the connection line 4, the above status signal is output. latch and hold.

The power supply control unit 4 connects the microprocessor 3 to the connection line 13.
The power-on signal supplied through the switch operates the relay to close the power-on/disconnect contact rat and connect wires 11 and 12.
and a status signal (first status signal) 'f of logic n I It is supplied to the register 6 via the connection line 15. In addition, a power cutoff signal supplied from the microprocessor 3 via the connection line 13 opens the relay and opens the power on/off contact rl to disconnect the connection lines 11 and 12, and also connects the connection line 15f to the register. A status signal (second status signal) of logic H□It is supplied to 6. Furthermore, when the power supply control unit 4 receives a power-on signal from the microprocessor 3, it waits a certain period of time after the supply time of the status signal, and when it receives a power-off signal, it simultaneously sends the status signal and waits for a certain period of time. Connect the microprocessor reset signal to wire 1
4 to the microprocessor 3 and register 6. The reason why the microprocessor reset signal is supplied after a certain period of time after the status signal is supplied when the power-on signal is received is to ensure smooth handling in the event that an abnormal condition occurs immediately after the power is turned on. .

The power supply section 8 is supplied with power via the connection line 12, generates the necessary power for the information processing device 1, and supplies it to each section. being monitored.

Clock section 9id is a circuit that generates time data every moment.

Next, the operation of this embodiment will be explained by dividing it into the following two steps.

1) From when the information processing device 1 is not in use to turning on the power 2) From using the information processing device 1 to turning off the power First, in the first step, when the information processing device 1 is not in use, the power on/off contact rl ! Please open the information processing device 1.
is not supplied with power, while power is supplied to the power supply control device 2 via the connection line 11f. Further, the status signal via the connection line 15'ft is a logic 1lOI, and the microprocessor which accesses the status determination program stored in the storage unit 5 in the initial state and reads that the value of the register 6 is a logic 1011. 3
accesses the automatic power-on program in the storage unit 5 and operates accordingly.

When the power-on time data reserved in the storage unit 5 and the time data in the clock unit 9 match and match, that is, when the reserved power-on time has arrived, the microprocessor 3 A power-on signal is supplied to 4 through the connection line 13.

The power control unit 4 receives the power-on signal from the microprocessor 3, closes the power-on/disconnect contact rl, fully connects the connection lines 11 and 12, and fully supplies power to the information processing device 1. At the same time, a logic l1II status signal is supplied via the connection line 15.

The microprocessor 3 diagnoses the power supply unit 8 that receives power supply via the connection line 13, and if an abnormality is detected within a certain period of time, the power supply control unit 4 diagnoses the power supply unit 8 that receives power supply via the connection line 13. A microprocessor reset signal is provided to register 6.

The register 6 latches the logic-2 status signal in response to the microprocessor reset signal, restores the status signal to the initial state in response to the microprocessor reset signal, and stores it in the storage unit 5. Access the program and register 6
It reads that the value of is logical ItIIf, accesses the storage section 7, and resumes operation according to the program stored in the storage section 7.

If an abnormality is found as a result of the diagnosis of the power supply unit 8 by the microprocessor 3, the abnormality processing is performed by the microprocessor 3 according to the automatic power-on program stored in the storage unit 5. In step , an automatic power-on process is performed by an automatic power-on process program stored in the three-microprocessor storage unit 5.

Next, in step 2, Fi power is supplied to the information processing device, and power is also supplied to the power supply control device 2. In addition, the status signal via the connection line 15 is a logic
11, the microprocessor 3 restores to the initial state by the microprocessor reset signal, accesses the status determination program stored in the storage unit 5, reads the value of the register 6, and recognizes this, as described above. The information processing apparatus 1 is operated by a program stored in the storage unit 7 for predetermined processing (including automatic power-off processing) necessary for the information processing apparatus 1 .

Communication control processors, input/output processors, service processors, etc. are used to improve the price/performance ratio by distributing all the functions of a computer system and using dedicated processors that can perform the most efficient processing. With the development of technology, microprocessors are being applied to each of the above-mentioned processors, and furthermore, microprocessors have been used in peripheral device control devices from an early stage.

The predetermined processing necessary for the information processing device 1 includes the communication control processing, input/output control processing, service function processing, etc., and any of these programs may be stored in the storage unit 7. , the microprocessor 3 can perform the processing. For this purpose, the connection line 13 naturally connects the microprocessor 3 with equipment in the information processing device 1 necessary for this processing.

A description will be given of when the information processing device 1 is used and the power is turned off.

When a power-off request is input from the information processing device 1 to the microprocessor 3 via the connection line 13, or when the power-off time data and clock section are reserved in a storage section (not shown) in the information processing device 1, 9, and if they match, t/C supplies a power cutoff signal from the microprocessor 3 to the power supply control section 4, and the power supply control section 4 thereby closes the power on/off contact r/! R is opened to cut off the power supply to the information processing device 1, and at the same time as the status signal via the connection line 15f is set to logic "o II Jtc", the power supply control unit 4 sends a microprocessor reset signal to the microprocessor 3 and the register 6 via the connection M14f. supply.

The register 6 latches the status signal of logic "011" in response to the microprocessor reset signal, and the microprocessor 3 restores to the initial state in response to the microprocessor reset signal and accesses the status determination program stored in the storage unit 5. It reads that the value of the register 6 is logic II Oll, accesses the automatic power-on program stored in the storage unit 5, and resumes operation.

When the microprocessor 3 receives an abnormality report, the microprocessor 3 performs abnormality processing according to the processing program stored in the storage unit 5.

As described above, in the second step, the microprocessor 3 executes the processing program stored in the storage unit 7.
Performs some processing necessary for the information processing device 1, including automatic power-off processing.

As described above, in this embodiment, when the information processing device 1 is in use, the microprocessor 3 follows the program stored in the storage unit 7 and takes over some of the processing necessary for the information processing device 1. It operates as a dedicated processor for the processing, improving the price/performance ratio of the information processing device, and when the information processing device 1 is not in use, it automatically follows the program stored in the storage unit 5. Power-on processing 1
4-, which contributes to labor saving.In the conventional device, all separate microprocessors were used, but the program that controls the microprocessor 3 when turning on and off the power is now controlled by a microprocessor reset signal. The microprocessor 3 accesses the status determination program stored in the storage unit 5 after restoring to the initial state, reads and recognizes the status signal held in the register 6, and uses the switch to reduce the number of microprocessors. can do.

As described above, in the present invention, when performing automatic power control, by switching between programs that control the microprocessor before and after power-on to the information processing device, a single microprocessor can perform automatic power-on processing as well as automatic power-on processing. This has the advantage that other necessary processing can be performed after the information processing apparatus is powered on, thereby reducing the number of microprocessors used in the information processing system.

[Brief explanation of drawings]

The figure is a block diagram of one embodiment of the present invention. In the figure, 1... information processing device, 2...
...Power control device, 3...Microprocessor, 4...Power control unit, 5, 7...Storage unit, 6...Register, 8... ·····Power supply part,
9... Clock part, rl... Power on/off contact, 11-15... Connection wire.

Claims (1)

[Scope of Claims] A first storage means for storing an automatic power-on processing program and a status determination program for the information processing device;
- a second storage means for storing a predetermined processing program including an automatic power-off processing program for the information processing device; and a signal for holding a first and second status signal in response to a microprocessor reset signal. holding means; in response to the microprocessor reset signal, restoring to the initial state and accessing the status determination program to read the status signal sound held in the signal holding means; when the status signal is a first status signal; a microprocessor that operates according to a processing program stored in the second storage means when Kid is the second status signal, and operates according to an automatic power-on processing program stored in the first storage means when the second status signal is received; Powering on the information processing device in response to a power-on signal supplied from the processor, generating the first status signal and the microprocessor reset signal, and responding to the power-off signal supplied from the microprocessor. An automatic power supply control device comprising power supply control status signal generation means for cutting off power to the information processing device and generating a second status signal and the microprocessor reset signal.