JPS58146948A - フアンクシヨンマクロ - Google Patents

フアンクシヨンマクロ

Info

Publication number
JPS58146948A
JPS58146948A JP57030326A JP3032682A JPS58146948A JP S58146948 A JPS58146948 A JP S58146948A JP 57030326 A JP57030326 A JP 57030326A JP 3032682 A JP3032682 A JP 3032682A JP S58146948 A JPS58146948 A JP S58146948A
Authority
JP
Japan
Prior art keywords
function
register
input
custom lsi
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57030326A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6221138B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Kenji Omori
健児 大森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57030326A priority Critical patent/JPS58146948A/ja
Publication of JPS58146948A publication Critical patent/JPS58146948A/ja
Publication of JPS6221138B2 publication Critical patent/JPS6221138B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP57030326A 1982-02-26 1982-02-26 フアンクシヨンマクロ Granted JPS58146948A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57030326A JPS58146948A (ja) 1982-02-26 1982-02-26 フアンクシヨンマクロ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57030326A JPS58146948A (ja) 1982-02-26 1982-02-26 フアンクシヨンマクロ

Publications (2)

Publication Number Publication Date
JPS58146948A true JPS58146948A (ja) 1983-09-01
JPS6221138B2 JPS6221138B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1987-05-11

Family

ID=12300681

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57030326A Granted JPS58146948A (ja) 1982-02-26 1982-02-26 フアンクシヨンマクロ

Country Status (1)

Country Link
JP (1) JPS58146948A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Also Published As

Publication number Publication date
JPS6221138B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1987-05-11

Similar Documents

Publication Publication Date Title
JP2699377B2 (ja) ハードウエア論理シミユレータ
US5594741A (en) Method for control of random test vector generation
EP0450839A2 (en) A logic simulation machine
JPH0230056B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPS5948424B2 (ja) 並列計算システム
JPS63145549A (ja) 論理回路シミユレ−シヨン方法
US5859962A (en) Automated verification of digital design
CN117290209A (zh) 测试用例生成方法、芯片验证方法、芯片验证系统和介质
US20060130029A1 (en) Programming language model generating apparatus for hardware verification, programming language model generating method for hardware verification, computer system, hardware simulation method, control program and computer-readable storage medium
JP2004348606A (ja) 高位合成装置、ハードウェア検証用モデル生成方法およびハードウェア検証方法
JP3737662B2 (ja) システムlsiのテストデータ最適化生成方式
JP3905951B2 (ja) シミュレーション/エミュレーションの効率を増すための論理変換方法
US4995037A (en) Adjustment method and apparatus of a computer
JPS58146948A (ja) フアンクシヨンマクロ
EP1187043A2 (en) Gate addressing system for logic simulation machine
US6339751B1 (en) Circuit design support apparatus and a method
JPH0429425Y2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPH0345580B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPS6311715B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPH0458070B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPH04225475A (ja) ロジック・シミュレーション・マシン及び処理方法
CN105446840A (zh) 一种Cache一致性极限测试方法
JP2003233632A (ja) ポインタ回路を備える集積回路装置および該集積回路装置の設計方法および設計支援装置
JP2797128B2 (ja) 論理シミュレータ
JPS6235699B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)