JPS58144958A - Shared memory controller - Google Patents

Abstract

PURPOSE:To avoid the breakdown of all systems, by breaking the power supply to one data processing system out of data processing systems consisting of plural data processors. CONSTITUTION:A foreshowing signal 10 for a power break is sent from a power source 2 to an FLUG 3 in a data processor 1 to set or reset the FLUG, and the address of a CONTROL STAGE 5 is controlled by a microprogram sequencer 4 and is sent to a data processing part 6. When the power supply is broken, the previous notice of the power break is displayed, and the power supply is broken after the elapse of a certain time. In this case, the time from the previous notice to the power break is made longer than the time from LOCK to LOCK release, and troubles due to the power break during this time are avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a shared memory control method, and in particular to a shared memory occupancy control method suitable for a data processing device system in which an abnormality in shared memory occupancy control seriously impedes system operation. Regarding the method.

In a data processing system consisting of multiple data processing devices as shown in FIG. Normally, control is performed, but by manipulating the shared memory, the second
As shown in Figure (a), when a certain data processing device uses a table in a shared memory, the contents of the table are displayed as occupied and prohibited from being used by other systems. Preventing confusion - In such table operations, as shown in Figure 2 (b), one data processing device occupies a certain table (
LOCK), and if the data processing device is powered off while its occupation is released (LOCK released),
A higher interrupt occurs and the table is occupied and the data processing unit goes down (HAW: HOlt).
and Wait), which makes it impossible to use it from other data processing devices, leading to the entire system going down.

An object of the present invention is to provide a device that prevents a shared table from being occupied when an abnormality occurs in a shared memory management system in a data processing system.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

As shown in Figure 3, a table on a shared memory connected to multiple data processing devices has an area containing error information (hereinafter referred to as a , LOCK).

Conventionally, access from a data processing device to a table on a shared memory is performed using a command (C
A8 instruction: Compare And 3 wop instruction)
Please make sure to check whether access is possible from the data processing device.

As an example of a system abnormality, the present invention will be described in detail in response to a power failure. At 9:00 a.m., a notice of power outage will be displayed, and after a certain period of time, the power will be cut off. In this case, as shown in Figure 6(a), the time from advance notice to power cutoff is longer than the time from LOCK to LOCK release, and the Problems can be avoided.

Next, in a case other than between LOCK and LOCK release, as shown in Fig. 6 Φ), the system branches to interrupt Goodaram processing with advance notice of power outage, turns on/off the flag during processing, and after interrupt processing. % Moving on to the CA8 instruction, as shown in Figure 5, the CAS
The above problem can be avoided by determining whether the flag is on or off at the beginning of the instruction, and if it is on, the data processing device is HAW'ed.

FIG. 7 shows an embodiment of the above-mentioned processing phase a.

From power supply 2 to PLUG 3 in data processing device 1, PO
Send P signal 10 (indicating power cutoff notice) and PLUG?
The microprogram sequencer 4 controls the address of the C0NTR0L8TRAGE 5 and sends it to the data processing section 6.

In the embodiment shown in FIG. 7, by performing the flows shown in FIGS. 5 and 6, it is possible to avoid the entire system from going down due to a power cut to the data processing device.

According to the present invention, it is possible to prevent the entire system from going down due to a power cut in one data processing system consisting of a plurality of data processing devices, thereby improving the reliability of the entire system. .

[Brief explanation of the drawing]

Figure 1 is a block diagram of a data processing system consisting of multiple data processing devices, Figure 2 (a), Φ) is a flowchart of shared memory operations, Figure 3 is a diagram of a table on the shared memory, and Figure 4 is the conventional CA8 instruction flowchart, @
Figure 5 is the new CA8 instruction flowchart of the present invention, No. 6
m-), Φ) are program flowcharts when the power is turned off,
FIG. 7 is a block diagram of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Data processing device, 2... Power supply, 3... Flag, 4... Micro program sequencer, 10...
・POP'41 B Figure 2 (4) <b) 3rd eye grass 5th eye 4th eye (^) Cb)

Claims (1)

[Claims] 1. Equipped with aiff data processing devices, a shared memory connected to each processing device and accessible from each, and a lock report that displays whether or not a table on the shared memory can be accessed, and shared management of the table. In a data processing system that performs this, there is provided a means for detecting that an abnormality has occurred in the In+ era data processing device, a means for branching to an interrupt program upon detection of the abnormality, and a flag for storing the presence of the abnormality. , wait for a mechanism to return to the original program before the interrupt, and perform interrupt processing using these; and at the beginning of the instruction to change the lock clearing storage, the flag is read, and if the flag is off, the If the lock information is pledged and the flag is on,
A way to stop writing to the lock information is to have an IR't-patent and a shared memory controller.