JPS60114929A - Control method of data storage device - Google Patents

Control method of data storage device

Info

Publication number
JPS60114929A
JPS60114929A JP22243183A JP22243183A JPS60114929A JP S60114929 A JPS60114929 A JP S60114929A JP 22243183 A JP22243183 A JP 22243183A JP 22243183 A JP22243183 A JP 22243183A JP S60114929 A JPS60114929 A JP S60114929A
Authority
JP
Japan
Prior art keywords
storage device
data
transfer
semiconductor storage
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22243183A
Other languages
Japanese (ja)
Inventor
Tatsuya Nakamura
達哉 中村
Atsushi Kimura
木村 惇
Takuo Toba
鳥羽 拓夫
Jiro Kubo
二郎 久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP22243183A priority Critical patent/JPS60114929A/en
Publication of JPS60114929A publication Critical patent/JPS60114929A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent destruction in a storage device by checking whether or not a data of a storage area corresponding to transfer is stored so as to transfer data. CONSTITUTION:A corresponding transfer area of a semiconductor storage device 2 is read from a control block 1. If the inside of the device 2 is in random state, a parity bit is set and interruption is generated by an interruption signal 7 in this case. An address of the semiconductor storage device 2 in which the parity bit is set is displayed by using a display device 5 in this interruption and a parity check flag is set. After the corresponding transfer entire area is read by a main program, if the parity check flag is not set, a data is transferred to a magnetic storage device 4 via a direct memory access control block 3 from the semiconductor storage device 2. When the flag is set, a message whether it is mis-operation or not is displayed on the display device 5.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、主記憶装置にダイナミックRAM等からなる
半導体記憶装置を用い、補助記憶装置に磁気テープ、フ
ロッピーディスク、バブルメモリ等の磁性体記憶装置を
用いるパーソナルコンピュータ、POSシステム等のデ
ータ記憶装置の制御方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention uses a semiconductor storage device such as a dynamic RAM as the main storage device, and a magnetic storage device such as a magnetic tape, floppy disk, or bubble memory as the auxiliary storage device. The present invention relates to a method of controlling data storage devices such as personal computers and POS systems.

従来例の構成とその問題点 半導体記憶装置と磁性体記憶装置とを有するシステム、
例えばストアードプログラム方式を取ってプログラムが
RAM上で動(POSシステムでは、前記プログラムを
半導体記憶装置であるRAMから磁性体記憶装置である
フロッピーディスク等にストアーする必要が往々にして
発生する。
Conventional configuration and its problems A system having a semiconductor memory device and a magnetic memory device,
For example, in a stored program system, a program runs on a RAM (in a POS system, it is often necessary to store the program from a RAM, which is a semiconductor storage device, to a floppy disk, which is a magnetic storage device, etc.).

ところが、操作ミスによ5RAM上に存在するプログラ
ムは、磁性体記憶装置ヘスドアーすべきプログラムでは
ないのにストアーしてしまったシ、顕著には電源投入直
後でRAM上のデータが全くランダムであるにもかかわ
らずストアーしてしまったりして、以前の磁性体記憶装
置内のデータを破壊してしまう恐れがあった。
However, due to an operational error, the program existing on the 5RAM was stored in the magnetic storage device even though it was not the program that should have been stored.This was especially true immediately after the power was turned on, and the data on the RAM was completely random. However, there was a risk that the data would be stored and the previous data in the magnetic storage device would be destroyed.

発明の目的 本発明は、電源投入後等の半導体記憶装置内のデータが
ランダムの状態の時に、半導体記憶装置内のデータを磁
性体記憶装置へ転送させるような操作ミスに対して、転
送の実行前に操作者に対して警告を与え、磁性体記憶装
置内のデータの破壊を防ぐことを目的とする。
Purpose of the Invention The present invention provides a method for executing transfer in response to an operational error such as transferring data in a semiconductor storage device to a magnetic storage device when the data in the semiconductor storage device is in a random state such as after power is turned on. The purpose of this is to warn the operator before the data is destroyed, thereby preventing the data in the magnetic storage device from being destroyed.

発明の構成 そのだめの構成として、本発明は、主記憶装置にグイナ
ミソクRAM等の半導体記憶装置を設け、補助記憶装置
に磁気テープ等の磁性体記憶装置を設け、前記半導体記
憶装置の転送に該当する記憶領域のデータが転送に値す
る状態に保持されていることをチェックした後に、前記
半導体記憶装置から前記磁性体記憶装置へデータを転送
するデータ記憶装置の制御方法である。
Structure of the Invention As a further structure, the present invention provides a main storage device with a semiconductor storage device such as a RAM, an auxiliary storage device with a magnetic storage device such as a magnetic tape, and which corresponds to the transfer of the semiconductor storage device. The method of controlling a data storage device transfers data from the semiconductor storage device to the magnetic storage device after checking that data in a storage area is maintained in a state worthy of transfer.

実施例の説明 第1図は、本発明の実施例のブロック図を示したもので
、第2図は本発明を実施するフローチャートを示したも
のである。
DESCRIPTION OF THE EMBODIMENTS FIG. 1 shows a block diagram of an embodiment of the invention, and FIG. 2 shows a flowchart for implementing the invention.

第1図において、′1はCP U (CentralP
rocessing Unit )を含む制御ブロック
、2はハIJティビットを有する半導体記憶装置、3は
DMA (Direct Memory Access
 )コントロールブロック、4は磁性体記憶装置、5は
表示装置、6はデータバスおよび制御信号、7は半導体
記憶装置2のパリティビットが立ったとき、制御ブロッ
ク1へ働きかける割込み信号線を示す。
In Figure 1, '1 is CPU (CentralP
2 is a semiconductor memory device having a high IJ bit, 3 is a DMA (Direct Memory Access)
) A control block, 4 a magnetic storage device, 5 a display device, 6 a data bus and control signals, and 7 an interrupt signal line that acts on the control block 1 when the parity bit of the semiconductor memory device 2 is set.

次に第2図のフローチャートに沿って半導体記憶装置内
のデータがランダム状態のとき、磁性体記憶装置へデー
タ転送させる操作ミスを未然に防ぐ方法を説明する。
Next, a method for preventing operational errors in transferring data to the magnetic storage device when the data in the semiconductor storage device is in a random state will be explained in accordance with the flowchart of FIG.

第1図の制御ブロック1から半導体記憶装置2の転送該
当領域をリードする。このとき半導体記憶装置2内がラ
ンダム状態であると、パリティビットが立ち、割込み信
号線7がアクティブになり、割込みが発生する。割込み
処理プログラムld表示装置5を用いて、パリティビッ
トが立った半導体記憶装置2上のアドレスを表示し、ま
たパリティチェックフラグを立てる。メインのプログラ
ムは半導体記憶装置2の転送該当領域全域のリード後、
割込み処理が発生したかどうかをパリティチェックフラ
グにより判断し、フラグが立っていなければ、半導体記
憶装置2がらDMAコントロールブロック3を・介して
磁性体記憶装置4ヘデータ転送させる。フラグが立って
いると、操作ミスかどうかの判断を操作者に問いかける
メソセージを表示装置6を介して表示する。パリティチ
ェックフラグが立っていても、転送するか否かを操作者
に問うのは、転送領域の一部だけデータをセットすれば
よい場合もあり得るからである。操作者は割込み処理プ
ログラムにより表示されたパリティビットの立ったアド
レスの情報を基に、転送をするか否かの判断を下す。
The transfer applicable area of the semiconductor memory device 2 is read from the control block 1 in FIG. At this time, if the semiconductor memory device 2 is in a random state, the parity bit is set, the interrupt signal line 7 is activated, and an interrupt is generated. Using the interrupt processing program LD display device 5, the address on the semiconductor storage device 2 where the parity bit is set is displayed, and a parity check flag is also set. The main program reads the entire transfer area of the semiconductor storage device 2, and then
Whether or not an interrupt process has occurred is determined by a parity check flag, and if the flag is not set, data is transferred from the semiconductor storage device 2 to the magnetic storage device 4 via the DMA control block 3. If the flag is set, a message is displayed on the display device 6 asking the operator to judge whether or not there was an operation error. The reason why the operator is asked whether or not to transfer data even if the parity check flag is set is because there may be cases where it is only necessary to set data in a portion of the transfer area. The operator makes a decision as to whether or not to transfer data based on information about addresses with set parity bits displayed by the interrupt processing program.

以上に示すように本実施例によると、半導体記憶装置内
のデータがランダムの状態のとき半導体記憶装置から磁
性体記憶装置への転送の操作ミスが生じても操作者によ
り取り消すことが可能となり、磁性体記憶装置内のデー
タを破壊することがない。
As described above, according to this embodiment, even if an operational error occurs during transfer from the semiconductor storage device to the magnetic storage device when the data in the semiconductor storage device is in a random state, the operator can cancel the transfer. Data in the magnetic storage device will not be destroyed.

発明の効果 以上のように本発明の制御方法によれば、操作ミスによ
る磁性体記憶装置内のデータの破壊を防ぐことが可能と
なるものである。
Effects of the Invention As described above, according to the control method of the present invention, it is possible to prevent data in a magnetic storage device from being destroyed due to operational errors.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のデータ記憶装置の制御方法を説明する
だめのブロック図、第2図は同制御方法のフローチャー
トである。 1・・・・・・制御ブロック、2・・・・半導体記憶装
置、3・・・・・・DMAコントロールブロック、4・
・・・・磁性体記憶装置、5・・・・・表示装置、6・
・・・・データバスおよび制御信号、7・・・・・・割
込み信号線。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第2図
FIG. 1 is a block diagram for explaining the method of controlling a data storage device of the present invention, and FIG. 2 is a flowchart of the same control method. 1... Control block, 2... Semiconductor storage device, 3... DMA control block, 4...
... Magnetic storage device, 5 ... Display device, 6.
. . . Data bus and control signals, 7 . . . Interrupt signal line. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2

Claims (1)

【特許請求の範囲】[Claims] 主記憶装置にダイナミックRAM等の半導体記憶装置を
設け、補助記憶装置に磁気テープ等の磁性体記憶装置を
設け、前記半導体記憶装置の転送に該当する記憶領域の
データが転送に値する状態を転送するデータ記憶装置の
制御方法。
A semiconductor storage device such as a dynamic RAM is provided as the main storage device, a magnetic storage device such as a magnetic tape is provided as the auxiliary storage device, and a state in which data in a storage area corresponding to the transfer of the semiconductor storage device is worthy of transfer is transferred. A method of controlling a data storage device.
JP22243183A 1983-11-25 1983-11-25 Control method of data storage device Pending JPS60114929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22243183A JPS60114929A (en) 1983-11-25 1983-11-25 Control method of data storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22243183A JPS60114929A (en) 1983-11-25 1983-11-25 Control method of data storage device

Publications (1)

Publication Number Publication Date
JPS60114929A true JPS60114929A (en) 1985-06-21

Family

ID=16782285

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22243183A Pending JPS60114929A (en) 1983-11-25 1983-11-25 Control method of data storage device

Country Status (1)

Country Link
JP (1) JPS60114929A (en)

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