JPS58144869U - Printed board - Google Patents
Printed boardInfo
- Publication number
- JPS58144869U JPS58144869U JP4044582U JP4044582U JPS58144869U JP S58144869 U JPS58144869 U JP S58144869U JP 4044582 U JP4044582 U JP 4044582U JP 4044582 U JP4044582 U JP 4044582U JP S58144869 U JPS58144869 U JP S58144869U
- Authority
- JP
- Japan
- Prior art keywords
- printed board
- circuit board
- printed circuit
- electronic
- pattern land
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例によるコンタクトピンとプリント基板の
はんだ付面との接触を示す断面図、第２図はそのプリン
ト基板のパターンランド、第３図は本考案の実施例によ
るコンタクトピンとプリント基板のはんだ付面との接触
を示す断面図、第４図はそのプリント基板のパターンラ
ンドとコンタクトピン専用パターンランドの図である。
１ニブリント基板、２：部品、３：はんだ付面、４：コ
ンタクトピン、５ニブリント基板のパターンランド、６
：コンタクトピン専用はんだ面、７：コンタクトピン専
用パターンランド。Fig. 1 is a sectional view showing contact between a contact pin and the soldering surface of a printed circuit board according to a conventional example, Fig. 2 is a pattern land of the printed circuit board, and Fig. 3 is a solder between a contact pin and a printed circuit board according to an embodiment of the present invention. FIG. 4 is a sectional view showing the contact with the attached surface, and is a diagram of the pattern land of the printed circuit board and the pattern land dedicated to contact pins. 1 Niblint board, 2: Components, 3: Soldering surface, 4: Contact pin, 5 Niblint board pattern land, 6
: Solder surface exclusively for contact pins, 7: Pattern land exclusively for contact pins.
Claims (1)
いて、前記プリシト基板のはんだ面に電子回路チェック
用コンタクトピンを接触させるための専用パターンラン
ドを設けたことを特徴とするプリント基板。1. A printed circuit board on which electronic components are mounted to form an electronic circuit, characterized in that a dedicated pattern land for contacting a contact pin for checking the electronic circuit is provided on the solder surface of the printed circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4044582U JPS58144869U (en) | 1982-03-24 | 1982-03-24 | Printed board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4044582U JPS58144869U (en) | 1982-03-24 | 1982-03-24 | Printed board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58144869U true JPS58144869U (en) | 1983-09-29 |
Family
ID=30051669
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4044582U Pending JPS58144869U (en) | 1982-03-24 | 1982-03-24 | Printed board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58144869U (en) |
-
1982
- 1982-03-24 JP JP4044582U patent/JPS58144869U/en active Pending
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