JPS58143377A - Liquid display panel - Google Patents

Liquid display panel

Info

Publication number
JPS58143377A
JPS58143377A JP57026976A JP2697682A JPS58143377A JP S58143377 A JPS58143377 A JP S58143377A JP 57026976 A JP57026976 A JP 57026976A JP 2697682 A JP2697682 A JP 2697682A JP S58143377 A JPS58143377 A JP S58143377A
Authority
JP
Japan
Prior art keywords
liquid crystal
display panel
voltage
video signal
driving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57026976A
Other languages
Japanese (ja)
Inventor
山崎 恒夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP57026976A priority Critical patent/JPS58143377A/en
Publication of JPS58143377A publication Critical patent/JPS58143377A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 この発明は、基叛上に液晶駆動用スイッチング索子ケマ
トリクス状に配置した数品表示パネルに関する〇 最近、従来のOf’lTに代わる表示装置として、薄型
の表示装置の開発が盛んに進めらnている。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to several display panels arranged in the form of a switching matrix for driving liquid crystals on a substrate.Recently, a thin display device has been used as a display device to replace the conventional Of'lT. Development is progressing actively.

薄型表示装置のなかでも、液晶表示装置は、消費電力、
駆動電圧々どの点で優nて29、今後の表示装置として
大きく期待されている。一般に液晶表示装置はダイナミ
ック駆動方式とスタティック駆動方式かあp%後省の万
が消費電力、駆動電圧。
Among thin display devices, liquid crystal display devices have low power consumption and
It is superior in terms of driving voltage and has great expectations as a future display device. In general, liquid crystal display devices use either dynamic drive method or static drive method to reduce power consumption and drive voltage.

駆動回路の簡単さなどの点で優扛ている。スタティック
駆動方式の液晶表示装置は一般に、上側ガラス基板と、
下側牛導体果績回路にマ) IJクス状に配W:芒nた
液晶駆動用素子會駆動回路で選択し、液晶に電圧?印7
JD’Tることにより、任意の文字、グラフあるいは画
像の衆示會行う。その一般的な従来の回路図ヶ第1図に
示す。
It is superior in terms of the simplicity of the drive circuit. Static drive type liquid crystal display devices generally have an upper glass substrate,
The lower conductor conductor is placed in the IJ square shape. W: Select the liquid crystal drive element in the drive circuit and apply voltage to the liquid crystal. Mark 7
By using JD'T, you can display any text, graph, or image to the public. A typical conventional circuit diagram is shown in FIG.

第1図は、スタティック駆動方式の液晶表示パネルに用
いる半導体集積(ロ)路基叛に液晶駆動用素子rマトリ
クス状に配置した回路図である。液晶駆動用スイッチン
グトランジスタ(MO8FKT)3はマトリクス状に量
産さnて寂り、2のケート信号鞠に電圧ケ印加テること
によυオン、オフできる。
FIG. 1 is a circuit diagram in which liquid crystal driving elements are arranged in a matrix on a semiconductor integrated circuit board used in a static driving type liquid crystal display panel. The liquid crystal driving switching transistor (MO8FKT) 3 is mass-produced in matrix form and can be turned on and off by applying a voltage to the gate signal of 2.

2のケート鞄に′…圧が刃口わって−るときに、1の映
像情号誉さ込み巌の電圧はオン状態のトランジスタ5ケ
辿して、キャパシタンス4に刃口わる。ゲート2ケ閉じ
ると、キャパシタンス4に刀aわった電圧は、仄の併き
替え時1で保愕芒扛、液晶セル5 i/(、印mさnる
。液晶セル中の液晶、′醒界効米型液晶、動的散乱効果
型の液晶は印/Jiれる電圧に尾、して白黒の濃淡表示
を行う。この方式は各液晶セルVCスタティックに電圧
を印加するので、低Y丙費電力、低電圧の駆動が可ぼヒ
になる。
When the voltage in the case 2 reaches a certain point, the voltage of the video information input signal 1 traces through the 5 transistors in the on state and reaches the capacitance 4. When the two gates are closed, the voltage applied to the capacitance 4 becomes 1 when the gates are replaced, and the liquid crystal in the liquid crystal cell 5 is turned off. The interfacial effect type liquid crystal and the dynamic scattering effect type liquid crystal display black and white gradation based on the applied voltage.This method has a low Y/C cost because voltage is applied statically to each liquid crystal cell VC. Power and low-voltage drive become weak.

しかし、半導体集積回路は#造工程が複雑であるため、
表革素子に用いる程度の大き芒(タテ、ヨコとも1筋以
上〜数副)に渡り欠陥なく作ることは非常に困難である
。この為画像信号印加用線1が断線または、基板とショ
ートするなどの欠陥が発生し得る。こnらの欠陥は画像
としては、線状の欠陥として現わ扛、実用上致命的な欠
陥となる。
However, since the manufacturing process of semiconductor integrated circuits is complicated,
It is extremely difficult to produce large awns (one or more to several lines both vertically and horizontally) without defects, such as those used for leather elements. For this reason, defects such as disconnection of the image signal application line 1 or short circuit with the substrate may occur. These defects appear as linear defects in the image, and are practically fatal defects.

本発明の目的は、従来の欠陥紮無くして、製造工程状1
発gE、全抑えることが困難な線状の欠陥會衆示上問題
の無い状態にすることである。
The purpose of the present invention is to eliminate the conventional defect ligation and to improve the manufacturing process.
The goal is to create a state where there is no problem in the appearance of linear defects that are difficult to completely suppress.

以下1図面により本発明の実施例葡評細に説明する。第
2図は、本発明の一夾例で、スタティック躯動万式の液
晶表示パネルに用いゐ半導体集積回路基板に、液晶駆動
用系子をマトリクス状に配置した回路図でるる。液晶部
類I用スイッチングトランジスタ(MOS FET )
5a、3b、5c、5d−。
Embodiments of the present invention will be described in detail below with reference to one drawing. FIG. 2 is a circuit diagram showing one example of the present invention, in which liquid crystal driving systems are arranged in a matrix on a semiconductor integrated circuit board used in a static and rotatable liquid crystal display panel. Switching transistor (MOS FET) for liquid crystal class I
5a, 3b, 5c, 5d-.

画像信号保持用キャパシタンス4a、4b、4c、4d
・・・はそnぞn液晶表示セル5a、5b、5c、5d
・・・・・・、ことにマトリクス状に配置にされている
。呆2図では、タテ×ヨコ−2×2の配属r示しである
が、一般にはタテ、ヨコとも任意の数、n X mの配
置でめる。
Image signal holding capacitance 4a, 4b, 4c, 4d
...Liquid crystal display cells 5a, 5b, 5c, 5d
In particular, they are arranged in a matrix. In Figure 2, the arrangement r is shown as 2 x 2 (vertical x horizontal), but in general it can be arranged in any number of n x m both vertically and horizontally.

隣りあう二本の氷水セル印加電圧用配線1a、Ibはそ
n−e扛、必るしきい値Vt以上の表示セル印加′電圧
でオン状態になる第二のスイッチ素子6a17aに接続
されており、6a、7aの出力は、スイッチングトラン
ジスタ3aに接続δ扛ている。
The two adjacent ice-water cell applied voltage wirings 1a and Ib are connected to a second switching element 6a17a which is turned on at a display cell applied voltage equal to or higher than the threshold value Vt. , 6a, 7a are connected to the switching transistor 3a.

6b、7b、6c、7c、6d、7d の谷スイッチ素
子も同様に、衣ホセル印7III′+![L圧用配?f
M1a、IJ Icに接続されているOg、晶駆動用ト
ランジスタ3a。
Similarly, the valley switch elements 6b, 7b, 6c, 7c, 6d, and 7d are also marked with the cloth mark 7III'+! [L pressure arrangement? f
M1a, Og connected to IJ Ic, crystal driving transistor 3a.

3b、5c、 3dのゲートn−tnぞれ2a、2bの
ケート鞠に接続さnている。
Gates 3b, 5c, and 3d are connected to gates 2a and 2b, respectively.

次に本発明の実施例について、動作方法ケ説明する。第
3図に各信号線に加える電圧のタイミング葡示す0テレ
ビ寺の画像を表示する場合、配線1aに時刻t1から1
.十△t7″T:映像信号會サンプリングした電圧か加
わる。配41j!1 bKは時刻、t1+△tからt1
+2Δt7で映像信号勿すンプリングした゛電圧か加わ
る。ゲート配線2aは映fJl!侶号が横方向に一ライ
ン走査する間(to〜tε)電圧Veか刃口わυ、トラ
ンジスタ3a、3b・・・・・・ iONにする0時刻
t1〜t1+△tの間1aに刃口わる′電圧が、トラン
ジスタ6aのスレショールド亀、 14’−V 7以上
であると6aはONになり、ON状態のトランジスタ5
 a 7.H通って映像信号はキャパシタンス4aに刃
口わる。次に時亥1]t1+△t−tl+2△tの間、
配線1bに加わる映像信号は、同様にしてVT以上の電
圧でろ扛は、トランジスタ7a會ブrして、キャパシタ
ンス4aに刀nわる。健って時刻t1+Δt〜〜 5− t1+2△tの映1家信号は時刻t1〜t】十△tの映
像信号?書き替えることになる。この様にし−C1キャ
パシタンス4 a Kは、−走査期11J中、二度映像
1g号が書き込7A、最後に書き込1れた映像信号が次
のフレーム周期で4き込77’ムる1で保持塾れゐ〇こ
の方法によると、仮に配線1aに欠陥がMつだ場合、1
aに加わる電圧が0に々9時時刻1〜t1+△t。
Next, the operating method of an embodiment of the present invention will be explained. Figure 3 shows the timing of the voltage applied to each signal line.When displaying an image of 0 TV temple, the timing of the voltage applied to each signal line is 1 from time t1 to wire 1a.
.. 10△t7″T: The voltage sampled from the video signal is added. Distribution 41j!1 bK is time, t1+△t to t1
At +2Δt7, the sampled voltage is applied to the video signal. Gate wiring 2a is film fJl! During one line scan in the horizontal direction (to to tε), the voltage Ve or the cutting edge υ, the transistors 3a, 3b...... The cutting edge is applied to 1a between the 0 time t1 and t1+△t when turning on iON. When the voltage exceeds the threshold voltage of the transistor 6a, 14'-V7, the transistor 6a turns ON, and the transistor 5 in the ON state turns on.
a7. The video signal passes through H and is transferred to the capacitance 4a. Next, during the time 1]t1+△t-tl+2△t,
Similarly, when the video signal applied to the wiring 1b is filtered at a voltage higher than VT, it is connected to the transistor 7a and is transferred to the capacitance 4a. Is the video signal at time t1+Δt~~ 5-t1+2Δt the video signal at time t1~t]10Δt? It will be rewritten. In this way, the C1 capacitance 4 a K is - During the scanning period 11J, the video signal 1g is written twice at 7A, and the video signal written lastly is 4 times 77' in the next frame period. According to this method, if there are M defects in wiring 1a, 1
The voltage applied to a becomes 0 at 9 o'clock time 1 to t1+Δt.

の間には、キャパシタンス4aK映像信号は書キ込了f
Lないか、時刻t】十△t〜t1+2△tの間に新しく
映像16号が誓き込″fnるのでキャパシタンス4aに
は欠陥とじて胡わnない。−万仮に、配線1bに欠陥が
有った場合、1bに〃口わる電圧が0になυ、時刻tl
+△t−t、、+2△t の間の映像16号はキャパシ
タンス4aには書き込1れない。しかし、時刻t1〜t
1+△t の間の映像は書き込1れている。
The capacitance 4aK video signal is written between f
L, time t] Since video No. 16 is newly inserted between 10△t and t1+2△t, there is no doubt that the capacitance 4a is defective. - In the unlikely event that the wiring 1b is defective. If there is, the voltage applied to 1b becomes 0 υ, time tl
Image No. 16 between +Δt-t, , +2Δt is not written to the capacitance 4a. However, from time t1 to t
The video between 1+Δt is written 1.

この様にして、仮に、ある画素にlkシあう一本の配l
IMが不良となっても、別の側の配線から映像信号が1
・き込1fLる。こ扛は隣り合92本の画素に同一の映
1縁伯号が書き込″!Fnるので、画面の分解能が部分
的に低下テるか、タテ、ヨコの分割aが 6− 100以上のマ) IJクス衆ボ装置は殆んど欠I伯ケ
意践することなく美しい画面が観察できる。テた、−1
血紮に連続して二度1天、イ岐イ8−号荀誓き込も・の
で、映像信号省き込み時間?^速化できる。
In this way, if one pixel corresponds to one pixel,
Even if the IM becomes defective, the video signal is still 1 from the wiring on the other side.
・Enter 1fL. In this case, the same image number is written in 92 adjacent pixels, so the resolution of the screen may be partially reduced, or the vertical and horizontal division a is 6-100 or more. Ma) The IJ Kushubo device is almost completely absent, and you can observe beautiful images without having to put any effort into it.Teta, -1
Two times in a row, Iqiyi No. 8-Xun Xun was also included in the blood ligature, so it was time to omit the video signal? ^It can be sped up.

以上、4・、ウヒ、明の実施例にL9、映像信号書き込
み配縁に欠陥がMつても、IIIu隊表示上、画質を大
きく劣化することの無い表示が司舵となる。了だ、映像
信号を回−画素に21比くり返し荀き込むので画素書き
込みt寺闇ン短、縮できる0 以上の説明で、第二のスイッチ素子6a 、 7a(第
2図)はPMO8,Nh40S等?仮定しているが、こ
tしらハ、トランスミッションケートなど一?のしきい
値以上のケート車圧でONする素子であnは艮い。また
半導体集積回路としてrよ、単結晶シリコン、ガラス板
上のアモルファスシリコン、多M市シリコンなど工pな
る薄膜トランジスタ、絶縁物暴根上の単結晶シリコンエ
pなる、薄膜トランジスタなどを用いることができるC
とは明らかでめる〇
As described above, even if there is a defect in the L9 and video signal writing arrangement in the embodiments of 4., Uhi, and Akira, the display that does not significantly deteriorate the image quality will be the control for the IIIu group display. OK, since the video signal is repeatedly applied to the pixel by 21 times, the pixel writing time can be shortened and reduced to 0. In the above explanation, the second switch elements 6a and 7a (Fig. 2) are PMO8, Nh40S. etc? I'm assuming, but what about a transmission cable? This is an element that turns ON when the vehicle pressure exceeds the threshold value. In addition, as a semiconductor integrated circuit, thin film transistors such as single crystal silicon, amorphous silicon on a glass plate, multilayer silicon, etc. can be used, and thin film transistors such as single crystal silicon on an insulator layer can be used.
It's obvious that

【図面の簡単な説明】[Brief explanation of the drawing]

釦、1し1は、従来の液晶駆動用素子tマド17クス状
IC配置した回路図、第2図は不兄明の液晶駆動用糸す
蓄マ) IJクス状に配置した回路図の一夾施例である
。第6図に、第2図の回路に双1わ◇電圧の時j…的f
勤を示″3−図である。 1、1a、 1b、 1c・・・・・・画gI倍号書き
込み1叡2.2a、2b、2cm−山−ケート慇3.3
a、3b、3c、3d・・・・・・ スイッチングトラ
ンジスタ4.4a、4b、4c、4d−・・用キャパシ
タンス5.5a、5b、5c、5d・=−@晶氷水セル
6a、6b、6Q、6d、7Q、7b、7J7d−=−
スイッチングトランジスタ 以   上 出願Δ 株寅会仕第 二釉工 合 第四 第 2 図
Button 1 and 1 are circuit diagrams of conventional liquid crystal drive elements arranged in a box shape, and Figure 2 is a circuit diagram of a conventional liquid crystal drive device arranged in a box shape. This is an example. Figure 6 shows that the circuit in Figure 2 has double 1 ◇ when the voltage is j...target f.
This is a 3-diagram showing the work. 1, 1a, 1b, 1c...Picture gI double number writing 1 2.2a, 2b, 2cm-mountain-Kate 3.3
a, 3b, 3c, 3d... Switching transistor 4.4a, 4b, 4c, 4d-... Capacitance 5.5a, 5b, 5c, 5d=-@Crystal ice water cell 6a, 6b, 6Q , 6d, 7Q, 7b, 7J7d-=-
Application for switching transistors and above

Claims (2)

【特許請求の範囲】[Claims] (1)  表示バ不ルケ構成する一方の基板に、液晶駆
動用スイッチング累子盆マトリックス状に配−した液晶
表示パネルに於いて、各液晶駆動用の第一のスイッチン
グ素子に、隣りあう二本の表示セル印加′亀圧用配稼が
、おの2の一定のしきい値以上の表示セル印7II11
IL圧でオン状態になる第二のスイッチ素子全弁して、
接続されていること全特徴とする液晶表示パネル。
(1) In a liquid crystal display panel in which switching elements for driving the liquid crystal are arranged in a matrix on one substrate constituting the display panel, two adjacent switching elements are connected to the first switching element for driving each liquid crystal. Display cell mark 7II11 where the voltage applied to the display cell is equal to or higher than a certain threshold value.
The second switch element, which turns on at IL pressure, has all valves,
It is connected to a full-featured LCD display panel.
(2)  第二のスイッチング索子UMO8)ランジス
タエリなること全特徴とする特肝詣ボの範囲第1項記載
の液晶表示パネル。
(2) The liquid crystal display panel according to item 1, characterized in that the second switching element UMO8) is a transistor element.
JP57026976A 1982-02-22 1982-02-22 Liquid display panel Pending JPS58143377A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57026976A JPS58143377A (en) 1982-02-22 1982-02-22 Liquid display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57026976A JPS58143377A (en) 1982-02-22 1982-02-22 Liquid display panel

Publications (1)

Publication Number Publication Date
JPS58143377A true JPS58143377A (en) 1983-08-25

Family

ID=12208183

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57026976A Pending JPS58143377A (en) 1982-02-22 1982-02-22 Liquid display panel

Country Status (1)

Country Link
JP (1) JPS58143377A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60242495A (en) * 1984-05-17 1985-12-02 セイコーエプソン株式会社 Active matrix panel
JPS6145280A (en) * 1984-08-10 1986-03-05 日本電信電話株式会社 Image display unit
JPS61243486A (en) * 1985-04-19 1986-10-29 松下電器産業株式会社 Active matrix substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60242495A (en) * 1984-05-17 1985-12-02 セイコーエプソン株式会社 Active matrix panel
JPH0785195B2 (en) * 1984-05-17 1995-09-13 セイコーエプソン株式会社 Active matrix panel
JPS6145280A (en) * 1984-08-10 1986-03-05 日本電信電話株式会社 Image display unit
JPS61243486A (en) * 1985-04-19 1986-10-29 松下電器産業株式会社 Active matrix substrate

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