JPH1097224A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve halftone display quality by reducing a write-in voltage itself of an analog sample-hold circuit and reducing an absolute value of a write-in error. SOLUTION: A switch element 23i (i=1-n) is opened before the switch element 21i (i=1-n) is opened, and a video signal 90 is written in, and precharge signal potential is written in a signal line 23i , and when the precharge is ended, the switch element 21i is opened, and the normal video signal 90 is written in. AC drive is performed by repeating this operation while changing the polarity of the video signal 90 and the precharge signal potential at every 1H. Signal line potential is precharged to the precharge signal potential beforehand by using a precharge signal line 15 and the switch element 22i (i=1-n), and thereafter, real video signal potential is written in. Then, e.g. when the precharge signal potential is made an intermediate value of video signal amplitude, the value of the write-in voltage becomes from 10V to 2.5V, that is, to 1/4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device used for OA equipment and the like, and more particularly to a high-resolution large-size direct-view liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, in a direct-view large-sized liquid crystal display device, only a switch element in a pixel portion is an amorphous-silicon TFT (Thin Film Transistor).
And a drive circuit using an external LSI was generally used. However, if the drive circuit can be integrally formed on the same substrate, advantages such as reduction in width outside the display portion, reduction in thickness, and reduction in cost arise. ing.

FIG. 8 shows an equivalent circuit diagram of a conventional driving circuit integrated type liquid crystal display device. The liquid crystal display device shown in FIG. 8 is disclosed in Japanese Examined Patent Publication No. 3-34273, and has a driving circuit integrated type using a polysilicon TFT and is used for a small panel such as a viewfinder.

In FIG. 8, signal lines 23 ₁ ,... 23 _n and scanning lines 32 ₁ ,.
2 _m are wired in a matrix, and these signal lines 23 _i
At the intersection of (i = 1,... N) and the scanning line 32 _j (j = 1,... M), a pixel electrode 36 is formed via a switch element 35. A counter electrode 37 is formed on a second electrode substrate (not shown) so as to face the pixel electrode 36, and a liquid crystal is formed by sandwiching a liquid crystal between the first and second electrode substrates. .

In this liquid crystal display device, an analog video signal 90 is supplied from the outside via a video signal line 10 and is written in an analog sample hold system. Video signal 10 is connected a switch element _{21 i (i = 1, ...} n) via the signal line 23 _i. The gate electrodes of the switch elements 21 _i (i = 1,... N) are connected to the signal line drive circuit 20. The gate signal 16 _i (i = 1,... N) is supplied from the signal line driving circuit 20 and the switching element 2
1 _1, ... by ON the 21 _n in sequence, it is possible to hold the video signal 90 in chronological order the signal lines 23 _1, ... 23 _n wiring capacitance 24 _1, ... to 24 _n. Scanning lines 32 _1, ... 32 _m are connected to the scanning line driving circuit 30, by supplying a scanning signal from the scanning line driving circuit 30, the signal lines 23 _1, time-series that is held in ... 23 _n The video signal 90 can be supplied to each pixel via the switch elements 21 ₁ ,..., 21 _n . Signal line drive circuit 2
By scanning the scanning line drive circuit 30 one stage at a time for each 0 scan, the video signal 90 can be supplied to all pixels. The electric field applied to the liquid crystal cell 38 is determined by the video signal supplied to each pixel, and the arrangement of the liquid crystal molecules in the liquid crystal cell changes depending on the magnitude of the electric field. For this reason, by combining with polarizing plates arranged above and below the liquid crystal cell, the intensity of transmitted light can be modulated and an image can be displayed. A storage capacitor 39 is separately formed on the pixel electrode 36 so that the pixel potential does not change during the holding period.

[0006]

In the conventional liquid crystal display device shown in FIG. 8, writing to the signal lines 23 _i (i = 1,... N) must be performed at the data rate of the video signal. The above operation method cannot be adopted in a direct-view type liquid crystal display device used for a computer or the like. This is because the panel size of the direct-view liquid crystal display device is about 10 inches diagonally, which is 100 times the area ratio of a small panel used for a viewfinder or the like (around 1 inch diagonal), and the signal line 23 _i (i = 1,... N), because the time constant of the video signal line 10 is increased by the area ratio, so that a sufficient writing time cannot be obtained within the data rate.

As a method for solving this problem, Japanese Patent Laying-Open No. 57-20129 proposes a method of dividing the video signal line 10 to lower the data rate of each signal line. However, when a large-sized, large-capacity liquid crystal display device is realized by increasing the number of video signal lines, if high-quality intermediate display is performed, the number of required video signal lines is greatly increased. According to the estimation of the present inventors, based on this method, for example, 12.1 inch XG of 256 gradation display
A (Extended Video Graphic)
Array) To realize a panel, the number of divisions is R
Each of the GB has 81 phases, for a total of 243 phases, and the video signal lines have 24
It becomes three. For this reason, there arises a problem that the circuit width of the built-in drive circuit increases, and a huge external circuit is required to supply each video signal line.

The present invention has been made in view of the above circumstances, and provides a liquid crystal display device capable of large-capacity and high-quality intermediate display without increasing the number of video signal lines as much as possible. The purpose is to do.

[0009]

A liquid crystal display device according to the present invention comprises a plurality of signal lines and a plurality of scanning lines arranged in a matrix, and first intersections between the signal lines and the scanning lines.
A first electrode substrate having a pixel electrode formed via the switch element, a second electrode substrate having a counter electrode formed to face the pixel electrode, the first electrode substrate and the first electrode substrate. A liquid crystal layer sandwiched between the first and second electrode substrates;
A video signal line for supplying a video signal, a precharge signal line to which a predetermined precharge potential is supplied, and first and second control signals at a predetermined timing corresponding to each of the plurality of signal lines. A control signal output circuit for outputting, and a plurality of control signal output circuits provided corresponding to each of the plurality of signal lines, for supplying the video signal to a capacitor added to the corresponding signal line based on the first control signal. And a plurality of second switch elements provided corresponding to each of the plurality of signal lines for supplying the precharge potential to a capacitor added to the corresponding signal line based on the second control signal. Wherein the potential of the precharge signal line is a constant potential between a black level and a white level of the potential of the video signal supplied to the video signal line. .

Preferably, the precharge potential is inverted in synchronization with the polarity of the video signal potential supplied to the video signal line.

Further, it is preferable that the precharge potential is a potential at which the transmittance of the liquid crystal cell becomes about half the white level.

Further, it is preferable that the power supply device further include voltage supply means for supplying a voltage to the precharge signal line, and the voltage supply means has a voltage adjusting function.

Preferably, there are a plurality of the video signal lines, and each of the second switch elements is connected to any one of the plurality of video signal lines.

It is preferable that a plurality of the precharge signal lines exist, and each of the third switch elements is connected to any one of the plurality of precharge signal lines.

[0015] In addition, in the second horizontal scanning period, the second
Preferably, the opening and closing of the switch element is performed after the opening and closing of the third switch element.

It is preferable that the open / close period of the third switch element is longer than the open / close period of the second switch element.

Preferably, the polarity of the video signal applied to the signal line is inverted every horizontal scanning period.

Further, it is preferable that the second and third switch elements are thin film transistors using polysilicon as an active layer.

Further, it is preferable that the second and third switch elements are CMOS switches.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment of a liquid crystal display device according to the present invention.
FIG. 1 shows an equivalent circuit diagram of the embodiment. The liquid crystal display device of this embodiment is different from the conventional liquid crystal display device shown in FIG.
_1, in which newly provided a ... 22 _n.

The precharge signal line 15 is supplied from the pre-charge signal supply circuit intermediate potential V _pp between black and white levels of the potential of the video signal 90 to be supplied to the video signal line 10 is not shown I have. Switch element 22
_{i (i = 1, ... n} ) is a NMOS-TFT, on the basis of the gate signal 17 _i sent from the signal line driving circuit 20, the signal line potential V _pp of the precharge signal line 15 2
3 _i .

In the liquid crystal display device of this embodiment, the switching elements 21 _i (i = 1,... N) and 22 _i (i
= 1,... N) and 35, a polysilicon thin film transistor (hereinafter also referred to as a poly-Si TFT) is used.
High-speed operation is possible. The drive circuits 20 and 30 are integrally formed on the first electrode substrate using a poly-Si TFT.

Next, the operation of the liquid crystal display device of the above embodiment will be described with reference to FIG. FIG. 2 shows one signal line 23 _i
A timing chart showing potential changes of (i = 1,... N) shows an example of the case of H-line inversion driving in which the polarity of the video signal 90 is inverted every horizontal scanning period 1H. FIG.
, V _BP , V _PP , and V _WP respectively represent a black level voltage, a precharge signal potential, and a white level voltage in the case of positive polarity, and V _BN , V _PN , and V _WN represent black level voltages in the case of negative polarity, respectively. , A precharge signal potential, and a white level voltage.

The white level voltage is an applied voltage when the liquid crystal has the highest transmittance, and the black level voltage is an applied voltage when the liquid crystal has the lowest transmittance.

In the case of the H line inversion drive, the signal line 23
_Since the effective potential of _i (i = 1,..., n) is substantially equal to the opposite potential, display deterioration such as crosstalk hardly occurs.
Since the polarity of the video signal 90 written to the data line is inverted every time, a large write voltage V needs to be written in the conventional liquid crystal display device as shown in FIG. 8, and a write error increases.

On the other hand, in the present embodiment, before the switching element 21 _i (i = 1,... N) is opened and the video signal 90 is written, the switching element 23 _i (i = 1,. , write precharge signal potential V _pp to the signal line 23 _i, at the stage of finished pre-charge, the switch element 21
_{Open i} and write a regular video signal 90. Performing AC driving by repeated while changing the operation of the polarity of the video signal 90 and a precharge signal potential V _pp for each 1H.

Generally, the write error ΔV of the analog sample and hold circuit is determined by the time constant τ of the sample and hold circuit,
The write time T and the write voltage V are obtained by the following equation.

ΔV = V / exp (−T / τ) (1) As a typical example, a conventional 12.1 inch XGA
The design result of the inventors about a panel is shown. Time constant τ
The wiring resistance R1 of the video signal line including the wiring from the input unit is 2 kΩ, and the ON resistance R2 of the switching element is 2
kΩ, the wiring capacitance C1 of the signal line is 50 pF, and τ = (R1 + R2) × C1 = 200 (ns) (2) The write voltage V is 10 (V) max when the liquid crystal is exchanged with an amplitude of 5 V. Therefore, in order to suppress the error ΔV to 256 gradations or less of the amplitude of 5 V, the write time T must satisfy the following condition. is there.

T ≧ τ · ln (V / ΔV) 〜1.25 (μs) (3) Since the writing time T is a value obtained by multiplying the reciprocal of the data rate f (65 MHz) by the number N of video signals, N = T · f〜81 (4), which means that a total of 243 video signal lines are required for 81 RGB colors.

[0030] In contrast, in the liquid crystal display device according to this embodiment the precharge signal line 15 and the switch element _{22 i (i = 1, ...} n) to use the signal line potential in advance to a precharge signal potential V _pp Precharge and then write the actual video signal potential. Therefore, for example, when the precharge signal potential is set to an intermediate value of the video signal amplitude, the value of the write voltage V becomes 1/4 from 10V to 2.5V. At this time, the writing time T is 0.90 from the equation (3).
μs, and the number N of video signals is 58 from the equation (4).

In practice, the relationship between the video signal voltage and the transmittance of the liquid crystal cell is not linear, but is VT (voltage-voltage) as shown in FIG.
(Transmittance) characteristic, the value of N can be further reduced by bringing the precharge signal voltage near the center of the VT curve shown in FIG.

Since the change in the transmittance with respect to the signal voltage is small in the flat portion of the VT curve shown in FIG. 3, considering only the range in which the change in the transmittance with respect to the signal voltage in the center is large, the voltage range is the precharge signal voltage. At ± 1 V, the write voltage V becomes 1 V, and at this time, the write time T
Is 0.79 μs from the equation (3), and the number N of video signals is (4)
It becomes 51 from the formula.

As described above, according to the liquid crystal display device of the present embodiment, the write voltage itself of the analog sample and hold circuit can be reduced, and the absolute value of the write error can be reduced. Therefore, the writing time can be reduced, and the number of video signal lines can be reduced. When the number of video signal lines is not changed, the halftone display quality can be improved by reducing the writing error.

In the present embodiment, the case of the H-line inversion drive has been described as an example. However, the same effect can be obtained in the case of the dot-inversion drive in which the H-line inversion drive and the V-line inversion drive are combined. Can be.

Next, a method of manufacturing the liquid crystal display device of the above embodiment will be described with reference to FIG. (A) First, an amorphous silicon thin film 51 having a thickness of 50 nm is deposited on a transparent insulating substrate 50 by a plasma CVD method.
Annealing is performed with an eCl excimer laser device to form polycrystals. The laser beam 52 from the excimer laser device is directed in the direction from the drive circuit formation region to the pixel portion formation region (FIG. 4).
The region (including the pixel portion forming region) scanned in the direction A shown in FIG. 4A and irradiated with the laser beam is crystallized to be a polycrystalline silicon film 53 (see FIG. 4A). At this time, by performing laser irradiation more than once while increasing the laser irradiation energy stepwise, hydrogen in the amorphous silicon film 51 can be effectively removed, and ablation during crystallization can be prevented. Irradiation energy is 200-500mJ
/ Cm ² . (B) Next, the polycrystalline silicon film 53 is patterned by photolithography to form an active layer 54 of the thin film transistor (see FIG. 4B). (C) After a gate insulating film 55 made of a silicon oxide film is formed by a plasma CVD method, a molybdenum-tungsten alloy film is formed by a sputtering method and patterned to form a gate electrode 56 (FIG. 4C). reference). At the time of this patterning, a scanning line is also formed at the same time. In addition, a silicon nitride film or a silicon oxide film formed by a normal pressure CVD method can be used as the gate insulating film 55.

After forming the gate electrode 56, the gate electrode 5
Impurities are implanted by ion doping using the mask 6 as a mask to form source / drain regions 54a of the thin film transistor (see FIG. 4C). As impurities, phosphorus was used for an N-channel transistor, and boron was used for a P-channel transistor. For the transistors in the pixel section, LDD (Lightly Do
It is effective to use a ped drain structure. in this case,
After the impurity is implanted into the source / drain portion 54a, the gate electrode is re-patterned to reduce the thickness by a certain amount, and then the low concentration impurity is implanted again. (D) Next, an interlayer insulating film 57 of a silicon oxide film is formed on the gate electrode 56 by a plasma CVD method or a normal pressure CVD method.
Is formed, and ITO (Indlum Tin) is formed on the interlayer insulating film 57.
Oxide) A film 58 is formed and patterned to form a pixel electrode 58 (see FIG. 4D). (E) Next, after forming a contact hole 59 in the interlayer insulating film 57 and the gate insulating film 55, an Al film is formed by a sputtering method and patterned to form a source / drain electrode 60. At this time, signal lines are also formed at the same time.

A first electrode substrate is completed by forming and patterning a passivation film as required. Note that the analog buffer circuit is formed in a drive circuit formation region on the first electrode substrate.

The first electrode substrate and the second electrode substrate on which the common electrode is formed are opposed to each other, the periphery thereof is surrounded by a sealing material made of epoxy resin, and liquid crystal is injected and sealed therein, thereby obtaining a liquid crystal display device. Become.

In the liquid crystal display device of the above embodiment, the driving circuit is formed integrally on the first electrode substrate using a poly-Si TFT. However, when the driving frequency is high and it is difficult to form the integrated circuit, the driving circuit is formed. Part of the circuit can be separately formed by an LSI process using single crystal silicon. In this case, it may be mounted on the first electrode substrate or TAB (T
ape Automated Bonding).

Next, the configuration of the signal line driving circuit 20 used in the liquid crystal display device of the above embodiment will be described with reference to FIGS. FIG. 5 is a partial equivalent circuit diagram of the signal line drive circuit 20, and FIG. 6 is a timing chart of the signal line drive circuit 20.

The signal line drive circuit 20 includes a shift register 20a composed of a clocked inverter, a NAND circuit 20b, and inverters 20c, 20d and 20e (see FIG. 5). Then, as shown in FIG. 6, a gate signal 17 _i for controlling the opening and closing of the switch element 23 _i (i = 1,... N) is applied prior to a gate signal 16 _i for controlling the opening and closing of the switch element 21 _i. . Since the pulse width of the gate signal 17 _i is set to twice the 16 _i, it is possible to perform the pre-charge with sufficient accuracy.

In the above case, the precharge time can be further increased by using the NOR circuit, and the switch elements 22 _i (i = 1,...) Are inversely proportional to the increase of the precharge time. The size of n) can be reduced.

In the liquid crystal display device of the first embodiment described above, the number of the video signal lines 10 and the number of the precharge lines 15 are one each. This will be described as an embodiment.

FIG. 7 shows a second embodiment of the liquid crystal display device according to the present invention.

The liquid crystal display of this embodiment is different from the liquid crystal display of the first embodiment shown in FIG. 1 in that two video signal lines 10 are used instead of the video signal line 10 and the precharge signal line 15. ₁ and 10 ₂ and two precharge signal lines 15 ₁ and 15 ₂ are newly provided.

The video signal lines 10 ₁ and 10 ₂ are connected to the video signal source 2
6 ₁ and 26 ₂ respectively. The precharge signal lines 15 ₁ and 15 ₂ are connected to the precharge signal supply circuit 40.
It is connected to the. One end is the ith signal line 23 _i
The other end of the switch element 21 _i connected is connected to the video signal line 10 _1, the other end of the switch element 22 _i whose one end is connected to the i th signal line 23 _i is the precharge signal line 15 ₁ It is connected to the. In this case the other end of the switch element 21 i _{+ 1,} which is connected to the signal line 23 i _{+ 1} adjacent are connected to the video signal line 10 _2, switching element 23
_{i + 1} of the other end is connected to a precharge signal line 15 _2.

Each switch element 21 _i (i = 1,...)
n) and 22 _i (i = 1,... n) are supplied from the signal line driving circuit 20. The precharge signal supply circuit 40 includes a switch circuit 42 including switches 42a and 42b for performing AC driving of the precharge signal potential, and positive and negative precharge signal sources 44 and 46. Reference numerals 44 and 46 allow the set voltage value to be changed in response to a temperature change or the like.

As described above, in the liquid crystal display device of the present embodiment, the band of the sample and hold circuit can be reduced by using a plurality of video signal lines. Further, by providing a plurality of precharge signal lines, for example, the AC inversion cycle of the precharge signal line potential for each clock required for dot inversion drive can be set to 1H,
It is possible to secure a time constant and reduce power consumption.

Note that the liquid crystal display device of the present embodiment is also the first liquid crystal display device.
Needless to say, the same effects as those of the embodiment can be obtained.

In the liquid crystal display device according to the second embodiment, the switch elements 21 _i and 21 _{i + 1} respectively corresponding to the adjacent signal lines 23 _i and 23 _{i + 1} are connected to different video signal lines. However, the present invention is not limited to this. Each of the switch elements 21 _i (i = 1,... N) may be connected to any one of the _two video signal lines 10 ₁ and 10 ₂ .

This relationship is based on the relationship between each switch element 22 _i (i =
1,... N) and the precharge signal lines 15 ₁ and 15 ₂ .

[0052]

As described above, according to the present invention, a large-capacity and high-quality intermediate display can be performed without increasing the number of video signal lines.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a first embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a timing chart of a signal line potential according to the first embodiment;

FIG. 3 is a graph showing characteristics of transmittance of a liquid crystal cell with respect to a video signal voltage.

FIG. 4 is a sectional view showing a manufacturing process of the liquid crystal display device according to the first embodiment.

FIG. 5 is an equivalent circuit diagram of a specific example of a signal drive circuit according to the liquid crystal display device of the first embodiment.

FIG. 6 is a timing chart showing the operation of the signal line driver circuit shown in FIG.

FIG. 7 is a configuration diagram of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 8 is an equivalent circuit diagram of a conventional liquid crystal display device.

[Explanation of symbols]

Reference Signs List 10 video signal lines 10 ₁ , 10 ₂ video signal lines 15 precharge signal lines 15 ₁ , 15 ₂ precharge signal lines 16 _i (i = 1,..., N) gate signals 17 _i (i = 1,..., N) gate signals 20 signal line drive circuit 21 _i (i = 1,... N) switch element 22 _i (i = 1,... N) switch element 23 _i (i = 1,... N) signal line 24 _i (i = 1,. ) Wiring capacitance 26 ₁ , 26 ₂ Video signal source 30 Scan line drive circuit 32 _j (j = 1,... M) Scan line 36 Pixel electrode 37 Counter electrode 38 Liquid crystal cell 39 Storage capacitance 40 Precharge signal supply circuit 42 Switch circuit 42 a , 42b switch 44 positive precharge signal source 46 negative precharge signal source 90 video signal

Claims (11)

[Claims] A plurality of signal lines arranged in a matrix,
A first electrode substrate having a plurality of scanning lines and a pixel electrode formed via a first switch element at an intersection of the signal line and the scanning line; and a first electrode substrate formed to face the pixel electrode. A second electrode substrate having a counter electrode; a liquid crystal layer sandwiched between the first electrode substrate and the second electrode substrate; a video signal line for supplying a video signal; and a predetermined precharge potential And a control signal output circuit that outputs first and second control signals at a predetermined timing in correspondence with each of the plurality of signal lines, and each of the plurality of signal lines And the first
A plurality of second switch elements for supplying the video signal to a capacitor added to the corresponding signal line based on the control signal of
A plurality of third switch elements for supplying the precharge potential to a capacitor added to the corresponding signal line based on the control signal of (c), wherein the potential of the precharge signal line is applied to the video signal line. A liquid crystal display device having a constant potential between a black level and a white level of a potential of a supplied video signal. 2. The liquid crystal display device according to claim 1, wherein said precharge potential is inverted in synchronization with the polarity of a video signal potential supplied to said video signal line. 3. The liquid crystal display device according to claim 1, wherein the precharge potential is a potential at which the transmittance of the liquid crystal cell becomes about half the white level. 4. The apparatus according to claim 1, further comprising voltage supply means for supplying a voltage to said precharge signal line, said voltage supply means having a voltage adjusting function. Liquid crystal display device. 5. The video signal line according to claim 2, wherein a plurality of said video signal lines exist.
Each of the switch elements is connected to any one of the plurality of video signal lines.
The liquid crystal display device as described in the above. 6. A plurality of precharge signal lines are provided,
6. The liquid crystal display device according to claim 1, wherein each of the third switch elements is connected to any one of the plurality of precharge signal lines. 7. The liquid crystal display according to claim 1, wherein the opening and closing of the second switch element within one horizontal scanning period is performed after the opening and closing of the third switch element. apparatus. 8. The liquid crystal display device according to claim 7, wherein the open / close period of the third switch element is longer than the open / close period of the second switch element. 9. The liquid crystal display device according to claim 1, wherein the polarity of the video signal applied to the signal line is inverted every horizontal scanning period. 10. The liquid crystal display device according to claim 1, wherein said second and third switch elements are thin film transistors using polysilicon as an active layer. 11. The second and third switch elements are C
2. A MOS switch, comprising: a MOS switch;
0. The liquid crystal display device according to any one of 0.