JPS58139460A - Read-exclusive memory - Google Patents

Abstract

PURPOSE:To improve the reverse withstand voltage of a storage transistor without deterioration of the characteristics of a transistor for a peripheral circuit by reducing the base density of a transistor for a memory cell to a value smaller than that of the transistor for the peripheral circuit. CONSTITUTION:An n type epitaxial layer 3 is superposed on a p type Si substrate 1 which has an n<+> type buried layer 2, connected via an n<+> type layer 31 to the layer 2, and a thermally oxidized film 61 is covered. Ions are selectively implanted to form p type bases 41, 42 and a connecting layer 43, and the impurity density of the layer 41 is reduced smaller than that of the layer 42. A CVD SiO2 film 62 is covered, holes 51, 32 are opened, an n type doped polysilicon 7' is accumulated, an n type emitter 5 is formed, and a polysilicon fuse 7 is formed on a memory cell transistor. After a hole 44 is opened, metal wirings 8 are formed. According to this configuration, only the VEBO of the memory cell transistor is improved, no influence is affected to the various characteristics of the transistors of the peripheral circuit, reverse breakdown of the non- selected memory cell transistor is eliminated at the writing time, thereby obtaining an ROM having high reliability.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor memory device with an emitter follower and an EF fuse (hereinafter referred to as an EF fuse). The present invention relates to programmable read-only storage devices.

[Technical background of the invention]

A part of the memory cell array and memory peripheral circuit of this stock read-only memory device is shown in FIG.

For convenience of explanation, the memory cell array 10 is constructed by arranging a wire with an IF and a wire 11 at the intersection of a matrix of two wires @11, 11 and two wires 13 and 14. It shows. 16 to 19 are 7-or transistors 69, transistors 16 and 77 have their respective paces connected to the word line 11, and their respective collectors are connected to the power supply V (at the time of writing! program voltage V % at the time of start-up) normally connected to the voltage V). To rWjil, each pace of the Torano C star 8.111 is connected to the word line 12, and each collector is connected to the power supply VKIII.

20 is a driver circuit 69 connected to word 911;
This is a pair of diodes z that decode the decode input signals DI, DI, etc. output from the address buffer.
x, xz (diodes connected to other decode input signals are omitted for simplicity) and 1iII of diode 22.
j is equipped with a resistor 24 connected at one end to the power supply and a word-
connected to the pace of transistor 11 that drives 11 9,
The anode of the diode 21 is the emitter of the transistor 23,
It was later established as Australia's #IR and connected to Ward IIJJ). This driver circuit 20 is configured such that the power supply V is -rar when writing r-r to the memory cell array 1#.
'im voltage V, (＾voltage)K), input DI becomes Heylepel@H#), diode 21.11 turns off, transistor JJ turns on and supplies the cell transistor pace current, input D1 goes from @H1 to low level @L”
When K returns, diodes 21 and 22 are on, transistor 2
3 is off, ko 0 @L' j! There is a possibility that the charge of the transistor IS can be pulled out by the diode 1'JJ when the transistor IS is turned on.

The driver circuit 2g is provided corresponding to the word 11111, is supplied with the decode output DI as an input, and is configured l1ljIIK with the driver circuit 20 described above.

On the other hand, this is an xg#i current sink circuit, in which the signal input CEI is supplied to the input terminal, and the Zener diode 2r with the polarity shown in the figure is connected to this input terminal, and this Zener diode 270 has one end connected to the input terminal. connected resistor 2
8, and the pace is connected to the other end of this resistor 28.

is grounded, and the collector is
It consists of nine tranzosters 2g connected to , and nine resistors 30 extending 1jkm between the pace and ground end of this trannostar 29 . In this current sink circuit 2#, when data is written, the input CEI becomes 'H', the Zener diode rzy is turned on, and the transistor 29 is turned on to form a path for the write current.

Is the current sink circuit 26' a beat? It is provided in correspondence with the current sink circuit 114, is supplied with a signal input CE, and has the same configuration as the current sink circuit 26 described above.

Note that each of the transistors 1 to 19 and the phase 15 in the memory cell array 10 is, for example, the second klK.
It has the structure shown.

In other words, Iris 2#! In J, 1 is p-type semiconductor substrate%
X tit n flow layer, J is a-type Evita medium layer, 4t'j pace image area, 5 is 2i, ta area, - is surface oxide layer, IFi heating layer made of polycrystalline silicon, 8 is gold core This is koji distribution, and other components are omitted from illustration.

In the first line of FIG. 1, we will consider the case where, for example, word line P-11 and pit line 13 are selected for write W#, and other word lines and bit lines Fi are not selected. The threshold voltage and the forward voltage drop of each diode are Vf, and the saturation voltage between the collector and the collector of transistor 2# is tvcm.
Assuming that the 1Lm level of s□7, input, is the ground potential,
pjlJJo potential is Vp-Vf, '7-)
'The potential of bulge 12 is a low potential Vf, py) & the potential of JJ is a low potential VCKIA? , B, and G @14 are electrically in a 70-ting state. As a result, since the transistor 16 has been selected, writing is performed on the fuse 15 connected to the terminal and terminal of this transistor 16.

On the other hand, the transistor (19 in this example) placed at the intersection of the unselected word line and bit line has a voltage potential (potential of voltage 14) of V, -2Vf,
Since the pace potential (the potential of the word line 11) is Vf,
A reverse voltage of V, -3Vf is applied between the emitters.

[Problems with background technology]

The reverse breakdown voltage v0° of the emitter base junction of the transistor 19 to which the above reverse voltage is applied is the reverse voltage V,
When it is smaller than -3Vf, reverse breakdown occurs. At this time: tli) Lannostar 19's EMI, Ri/Pace joint deterioration, and the 211th! ! Electrons are injected near the surface oxidation gg shown in 1, and the surface recombination current increases due to the inversion layer caused by the 9 electrons injected into p1, which may deteriorate the characteristics of the memory cell transistor 19, or even worse: The process and pace joint may be destroyed.

In order to prevent this, it is only necessary to improve the V of the memory cell transistor, and for that purpose, it is necessary to lower the peak am of impurities in the paste 4 which is in contact with the emitter region 5 of gza. , if the pace is lowered once, VC is the pace 11tL of the peripheral circuit, which is formed at the same time as the manufacturing process.
If the %h is below 9, its kf*4+1 property will be affected. Therefore, in order to obtain the same hf and characteristics as after the above-mentioned base decrease, it becomes necessary to deepen the diffusion depth of the pace (However, if the pace collector junction becomes deeper, In the case of the thin I epitaxial layer 3, the collector-base dominant breakdown voltage vc is 4I due to the influence of the autodoped layer.

decreases, and along with this, the collector voltage withstand voltage vc, decreases.

Said lower! The program voltage falls below V,
This may cause the inconvenience that the circuit may not operate.

On the other hand, if the pace diffusion layer is shallow, the concentration in the pace region 4 is low, causing Δnte-through, as described above! VC, for the program voltage vp. is in short supply. Additionally, by lowering the pace concentration, the pace region 40 column resistance increases, causing a decrease in the force that affects switching speed, the to-off frequency f.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is possible to reduce the reverse breakdown voltage V□ of the emitter/base junction of a cell transistor without deteriorating the transistor characteristics of the peripheral circuit. The purpose of this invention is to provide a read-only storage device that can increase the storage capacity.

[Summary of the invention]

In other words, the present invention provides an Ik degree of a pace region of a memory cell transistor and a degree II of a pace region of a peripheral circuit transistor.
) By making it different, the reverse withstand voltage vgm of the I and Pace junctions of the above two transistors is made different. The cell transistors are different. is the peripheral circuit transistor's V□.

By making the cell transistors more stable, deterioration and destruction of the cell transistors are prevented, as well as deterioration of the characteristics of the peripheral circuit transistors, so that memory operations can be performed without any trouble.

[Embodiments of the invention]

43 (1) to (d) and 114 (a) to 114 correspond to the manufacturing process 4m of cell transistors and peripheral circuit transistors of the read-only memory MW according to the present invention.
-) to make the first light.

(1) First, after selectively forming a 11+ field layer xtsa on a pm silicon substrate 1, a %all epitaxial layer 3 is grown. after that,? After forming the collector connection region Jlf, approximately 1
A thermal oxide film 61t of 001 is formed (JI3 figure a,
IIJ Diagram a#).

(2) Next, using an ion implantation method, the portion that will become the base region of the memory cell transistor is implanted with, for example, ion at an accelerating voltage of 75 keV%, followed by heat treatment at 1000°C for about 60 minutes. 1lt- is carried out to form a space region 41t- of the memory cell transistor (see FIG. 3).

He used an ion implantation method to the part that would become the pace region 42 of the peripheral l-path transistor, and set the accelerating voltage to 85, for example.
V, implantation amount 3 Form 421 (4th
Figure b).

(3) Next, after forming the external base contact region 43 using the ion implantation method in the same manner as described above, sio2g J is deposited using the CVD (chemical vapor deposition) method, and after baking and hardening, the Scattered hole 5 and collector contact 32t - form 0 then mHI! Emitter polycrystalline silicon 7' containing impurities.

Deposits in the Yuha scattering hole 51 and the collector contact 32,
After forming the emitter region 5, a polysilicon layer rt is formed on the cell transistor. Note that a common contact (not shown) 'fr is formed on the collector of each cell transistor (see FIG. 3C2 and FIG. 4).

(4) Next, the base contact 44 is drilled, and the metal connection is made! I#t-Apply (@see Figure 3 d, Figure 4 d).

The memory cell transistor and the peripheral circuit transistor manufactured as described above have different base rust layers, and the base rust layer of the memory cell transistor is smaller than the base 'a& of the peripheral circuit transistor, and In the *m example above, the V.0 of the memory cell transistor is approximately 1
9, the voltage of the peripheral circuit transistor is 0V. . (about 7v)
This has been improved compared to the dog.

〔Effect of the invention〕

As mentioned above, according to the present invention, V□ of the memory cell transistor. Since it does not affect the optimum value of each characteristic of the peripheral circuit transistor (vCl., ■3..# hfe */,), it does not slow down the memory operation, and the memory that is not selected at the time of writing can be The cell transistor does not undergo reverse breakdown between the emitter and base, so there is no deterioration of the memory cell transistor.
Two bipolar storage devices with good reliability can be provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing part of the memory cell array and peripheral circuits of a piler-type programmable sequential-only memory device, and the IZ diagram is an emulation of the #I1 diagram. 3(a) to 4(d) and 4(0))
-(d) are diagrams showing structures in the manufacturing process of memory cell transistors and peripheral circuit transistors in a read-only memory device according to the present invention. 4...Base region, 10...Storage cell array, 16
~79. jJ・) Rannosta, J O# J O'・
...Driver circuit. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 112 (e) (C) Procedural amendments dated June 8, 1972, Director of the Japan Patent Office Otojima 1) Tonoki No. 1, case display II axis Showa 57-22506? f.) Relationship with the case of the person who made the amendment to the storage device for exclusive use of the name of Yamei 3゜ Patent originator (307) Tokyo Shibaura Electric Co., Ltd. 4, Agent May 25, 1980 6, Drawings subject to amendment 7. Contents of the amendment Figure 4 of the drawings is corrected as shown in Attachment Drawing I: marked in red. □−−−=2211111] 1=West (C) Ichino□ ＾ & □ ■

Claims (1)

[Claims] A bipolar lid with a memory cell array and memory peripheral circuitry using heating elements with a Taphoroa as memory cells! In a p-rubrium-capable read-only memory device, the power of the transistor for the memory cell is smaller than that of the transistor for the peripheral circuit, and the reverse breakdown voltage of the Niotsuta-Pace junction is made higher. Storage device.