JPH02144961A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize a high-speed operation by a method wherein a base diffusion concentration of a bipolar element constituting a peripheral circuit of a bipolar RAM is set selectively at a high concentration with reference to a base diffusion concentration of a bipolar element inside a memory cell array. CONSTITUTION:In a semiconductor memory device 1 as a whole, a selective implantation operation of a p-conductivity-giving substance by using a mask is executed in two or more processes in order to form a base diffusion layer of a bipolar transistor. During a first selective implantation process, a mask 4 covering a memory cell array 2 wholly is used. The mask 4 used during this process is composed of a whole-face mask part 41 which covers the memory cell array 2 wholly and a selective mask part 42 which selectively exposes a base electrode extraction part inside a peripheral circuit 3. Since an ion implantation operation is blocked completely under the whole-face mask part 41, this part becomes a low-concentration base diffusion region 5; a part under the selective mask part 42 becomes a high-concentration base diffusion region 6. Thereby, it is possible to selectively set only a base region 8 of a bipolar transistor QB inside the peripheral circuit 3 at a high concentration; a high-speed operation can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technique that is effective when applied to semiconductor devices, and furthermore, to semiconductor memory devices. It is about effective techniques.

[Prior Art] In order to increase the speed of bipolar RAM, it is effective to reduce the base resistance of bipolar transistors, especially bipolar transistors that constitute peripheral circuits. It is necessary to increase the concentration of the conductivity-imparting substance in the base diffusion layer (for example, see Nikkei Electronics, April 6, 1987 issue (no. 418), p. 74.75, published by Nikkei McGraw-Hill).

Therefore, a conductivity-imparting substance such as boron is added to the base regions of all bipolar transistors in a semiconductor device in which a bipolar RAM is integrated by ion implantation called implantation. Thereby, the base diffusion concentration of the bipolar transistor can be increased, and the base resistance can be reduced to increase the speed.

[Problems to be Solved by the Invention] However, the inventors have found that the above-mentioned technique has the following problems.

In other words, if ion implantation is performed excessively in order to increase the speed by increasing the concentration of the base diffusion layer, crystal defects due to the ion implantation are likely to occur. The inventors of the present invention have revealed that this causes problems such as a decrease in yield and an increase in the probability of occurrence of defects.

Furthermore, the inventors have learned that the above-mentioned defects caused by ion implantation tend to occur in the portion of the memory cell array where a large number of bipolar transistors are arranged in high density. did. When a defect occurs in a bipolar transistor in a memory cell array, a partial memory defect called so-called bit drop occurs.

Although this bit loss is difficult to detect, it is highly disliked because it significantly impairs the reliability of devices and systems.

An object of the present invention is to provide a technology that can increase the operating speed of a semiconductor device in which a bipolar RAM is formed, for example, while reliably avoiding the occurrence of defects such as dropped bits. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, for example, the base diffusion concentration of bipolar elements constituting the peripheral circuit of a bipolar RAM is selectively made higher than the base diffusion concentration of bipolar elements in the memory cell array. That is what it is.

[Operation] According to the above-described means, the speed of the bipolar elements in the peripheral circuit, which has a large effect on the operating speed of the memory device, is increased by increasing the concentration of the base diffusion, while the bipolar elements in the memory cell array are The element can avoid occurrence of defects such as crystal defects due to an increase in the base diffusion concentration.

This achieves the object of, for example, making it possible to speed up the operation of a semiconductor device in which a bipolar RAM is formed, while reliably avoiding the occurrence of defects such as dropped bits.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows the schematic structure of a semiconductor device according to an embodiment of the present invention in terms of a planar layout.

The semiconductor device shown in the figure is configured as a semiconductor memory device 1 forming a bipolar RAM. This semiconductor memory device 1 includes a memory cell array 2 in which a large number of bipolar transistors are arranged at high density, and a peripheral circuit 3 configured using bipolar transistors, which are integrated within the same semiconductor substrate. .

The peripheral circuit 3 includes an X decoder 31 and an X driver 32.
, Y decoder 33, Y selection switch 34, storage data input circuit 35, sense circuit 36, storage data output circuit 37
etc. are arranged and formed around the memory cell array 2.

Here, as shown in FIG. 2, the base diffusion concentration of the bipolar transistor QB constituting the peripheral circuit 3 is:
The base diffusion concentration of the bipolar transistor QA in the memory cell array 2 is selectively increased.

In FIG. 2, QA and QB are npn-type bipolar transistors, 7 is a collector region formed by an n-type diffusion layer, 8 is a base region formed by a p-type diffusion layer, and 9 is an n-type bipolar transistor.
An emitter region formed by a type diffusion layer, C a collector electrode, B a base electrode, and E an emitter electrode, respectively.

The bipolar transistor QB constituting the peripheral circuit 3 has an electrode extraction portion of its base region 8.

Additional ion implantation of boron, which is a p-conductivity imparting substance (
The concentration is partially increased by implantation. 81
indicates the highly concentrated part. By reducing the base resistance due to this partial increase in concentration, the operation speed of the bipolar transistor QB is increased.

On the other hand, the base region 8 of the bipolar transistor QA constituting the memory cell array 2 has no high concentration portion formed by additional ion implantation. This prevents crystal defects from forming easily.

Here, bipolar transistor QB in 1 peripheral circuit 3
In order to selectively increase the concentration only in the base region 8 of
The following steps are performed.

That is, for the semiconductor memory device 1 as a whole, the selective implantation of the P conductivity-imparting material using a mask to form the base diffusion layer of the bipolar transistor is performed in at least two steps. At this time, as shown by the dotted line in FIG. 1, a mask 4 that completely covers the memory cell array 2 is used during at least one selective implantation process.

The mask 4 used at this time includes a full-face mask portion 41 that completely covers the top of the memory cell array 2, and selectively covers the base electrode extraction portion in the peripheral circuit 3, as shown by the dotted line in FIG. It consists of a selection mask section 42 to be exposed. Since ion implantation is completely blocked under the entire surface mask section 41, the region becomes a low concentration base diffusion region 5, and the region under the 1 selection mask section 42 becomes a high concentration base diffusion region 6. In other words, by using the mask 4 that implants ions except for the memory cell array 2, it is easy to selectively increase the concentration of only the base region 8 of the bipolar transistor QB in the peripheral circuit 3. can be done.

As described above, the bipolar transistor QB in the peripheral circuit 3, which has a large effect on the operating speed of the memory device, is made faster by increasing its base diffusion concentration, while the bipolar transistor QB in the memory cell array 2 Transistor QB can avoid crystal defects caused by high base diffusion concentration.

This makes it possible to increase the speed of operation while reliably avoiding the occurrence of defects such as dropped bits.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, the peripheral circuit 3 or the circuit in the memory cell array 2 may be a bipolar/CMO9Mt combination circuit, a so-called Bi-CMO8 circuit.

In the above explanation, the invention made by the present inventor was mainly applied to bipolar RAM, which is the background field of application. It can also be applied to semiconductor devices in which memories are formed.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, it is possible to increase the speed of operation while reliably avoiding the occurrence of defects such as missing bits in the memory formed in the semiconductor device. This effect can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a schematic configuration of a semiconductor device according to an embodiment of the present invention, and a diagram showing the configuration of an Ibora element. DESCRIPTION OF SYMBOLS 1...Semiconductor memory device, 2...Memory cell array, 3...Peripheral circuit section, 4...Mask used in the step of forming a base diffusion layer, 41... Full-face mask part, 42... Selected mask part, 5... Low concentration base diffusion region, 6... High concentration base diffusion region, QA
... Bipolar transistor in memory cell array 2, QB... Bipolar transistor in peripheral circuit 3, 8... Base region. 81...High concentration part.

Claims (1)

[Claims] 1. A semiconductor device in which a memory cell array in which a large number of bipolar elements are arranged at high density and a peripheral circuit configured using bipolar elements are integrated within the same semiconductor substrate. A semiconductor device characterized in that the base diffusion concentration of the bipolar elements constituting the peripheral circuit is selectively made higher than the base diffusion concentration of the bipolar elements in the memory cell array. 2. The electrode extraction portion of the base region of the bipolar element constituting the peripheral circuit is partially enriched by additionally implanting a conductivity imparting substance, as set forth in claim 1. Semiconductor equipment. 3. A method for manufacturing a semiconductor device in which a memory cell array in which a large number of bipolar elements are arranged at high density and a peripheral circuit configured using bipolar elements are integrated in the same semiconductor substrate, The selective implantation of the conductivity-imparting material to form the base diffusion layer of the bipolar element is performed in at least two steps, and during at least one selective implantation step, the memory cell array is 1. A method of manufacturing a semiconductor device, comprising using a mask that completely covers the semiconductor device.