JPS5813933B2 - multiprocessor control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory control device for a memory sharing multiprocessor system.

The prior art is shown in FIGS. 1 and 2.

In the system shown in Figure 1, the storage device (MS) JQuests from both central processing units (CPUs) are selected by the MS request selection device (SEL section), one is accepted, and the main storage device (MS) is activated. .

MS requests may collide in the SEL section,
This resulted in the MS request processing speed of each CPU being significantly lower than when it was single.

Figure 2 is a somewhat improved version of the method shown in Figure 1.
By having an S state management device (MSCTL section),
It manages the operating status of MS banks.

That is, for example, when an MSJ quest occurs on CPUo,
MSCTLo and MSCTL refer to the bank operation states of the MSs that they manage, and if both banks are empty, a boot is issued to the MS.

Data exchange between both CPUs and both MSs is performed using a data exchange device (
SW section).

With this method, MS requests generated by both CPUs can be activated only for empty banks, so M
There is no collision with S, and compared to the method shown in Figure 1, the CPU
The decrease in MSJ Quest processing speed compared to the single version is minimal.

In Figures 1 and 2, each MS has n banks (ways).
If so, by using a multiprocessor configuration, the MS can have 2n banks (ways) or more.

In FIG. 1, a configuration of 2n banks or more can be realized by increasing the number of CPUs and each SEL section.

However, since collisions in MSs are unavoidable, the performance of each CPU still suffers from a significant drop in performance due to multiprocessorization.

In Figure 2, a configuration of 2n banks or more can be realized by increasing SW, but in the conventional technology, the number of banks that can be managed by the MSCL section is the same as the number of MS banks in a single processor, so all MS banks can be managed at the same time. It is impossible to operate it, and when the MS bank status is referenced by MSCTL, there is a possibility that a waiting period will occur because the bank is empty, and the performance of each CPU due to multiprocessorization is still significant.

The purpose of this invention is to prevent MS requests from each CPU from colliding with each other in the MS bank in a multiprocessor with MS shares, and to enable all banks to operate simultaneously, thereby reducing the
An object of the present invention is to provide a multiprocessor control device that minimizes performance degradation of a PUi.

This invention improves the efficiency of MS usage by managing the MS bank status between both CPUs in the case of a multiprocessor, with the number of banks being twice that of a single processor (in the case of two CPUs).

For convenience of explanation of the embodiment, it is assumed that the multiprocessor has two CPUs and the number of banks of each MS is four.

This is only for convenience of explanation and does not detract from the generality of the invention.

Further, the data structure may be either shown in FIG. 1 or FIG. 2, and the data structure is not limited.

Here, a method for controlling MS requests, which is the gist of the present invention, will be specifically described.

FIG. 3 shows the MS request control logic in CPUo.

Subscript i indicates MSA, and subscript j indicates bank number. shows.

A and gate, OR is or gate, CPUo
Request “CPUoBKs-” to MSi-j from
When 3REQJ occurs, it is the MS request reception cycle (CPUoREQCYCLE) of CPUo and MSi-j is in the free state (BKi-j BSY='0') (latch (LTH output)), and the activation to the MS is performed. A signal is created (CPUoBKi-jREQ).

Here, the CPUoREQ CYCLE signal is a signal generated in synchronization with the CPU machine cycle.
Q It becomes III alternately with the CYCLE signal.

Further, the BKi-jBSY signal is set by the bank i-j activation signal from CPUo or CPU1 as shown in the figure, and is set by the MS cycle end signal (RESETBK BSYi
-j), and is a key signal for MS request control.

When the MS activation signal is created in this way, the MS bank status signals of both CPUs immediately become busy, so if 7 MSJ quests to the same bank occur in the CPU during the next CPU's MSJ quest cycle. Even if the activation signal is not generated again, no collision of requests occurs in the MS.

Furthermore, the MS can be used effectively by suspending requests to operating banks and processing requests to idle banks with priority.

Further, it is possible to process a block request preferentially by inhibiting activation of the block from another CPU to the bank at the same time as the block request is generated.

MS No. , (1), Bank No. An example of the selection of (j) is shown in FIG.

This is a 24-bit address and 8-byte depth, and bit 18 indicates MS No. , hit 19-20 and bank No. Choosing the right person is the town's Noh task.

In addition, MS No. The selection of is not limited to bit 18, but any bit among bits 0 to 19 is possible.

The present invention is realized by providing the logic shown in FIG. 3 in the MS request control section of each CPU for all MS banks in a multiprocessor configuration (in this example, 8 circuits for each CPU).

This invention makes it possible for the first time to eliminate MSJ Quest conflicts and operate all banks simultaneously by managing the operating status of the MS banks of the entire system for each CPU that makes up the multiprocessor. This makes it possible to minimize the performance deterioration per CPU due to

[Brief explanation of the drawing]

1 and 2 are block diagrams showing the configuration of a conventional multiprocessor system, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 is a block diagram showing the configuration of a conventional multiprocessor system. FIG. 2 is an address configuration diagram showing an example of usage. CPU...Central processing unit, MS...Storage device.

Claims (1)

[Claims] 1 In a multiprocessor system that shares a storage device, each central processing unit manages the operating status of all banks of connected storage devices, and each central processing unit keeps the memory in an empty state during the memory reception cycle of its own central processing unit. A multiprocessor control device characterized in that a certain storage device bank can be used, and at the same time, other central processing units are prohibited from using the same bank until the end of the storage device cycle.