JPS5813931B2 - Memory Busy - Kanrihoushiki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention comprises a plurality of main memory devices of different speeds and at least one
The present invention relates to a memory busy management method in an information processing system including two processing devices.

Conventionally, memory busy management has been carried out by means of an in-use display flip/flop provided in the processing unit corresponding to each main memory device, or a control line for in-use indication sent from each main memory device to the processing unit. A method has been adopted in which each main memory device to which access is requested is confirmed to be not currently in use, and then each access is permitted.

On the other hand, in information processing systems such as electronic exchanges, which require strict real-time performance and reliability, redundancy is required to prevent the system from going down even if a failure occurs in one of the devices that make up the system. It is common that the structure is

Now, in the main memory device of such an information processing system, when n main memory devices are required, one additional main memory device is required.
Incorporating the device into the system as a backup device, so-called n
Considering the case where a +1 redundant configuration is adopted, it becomes necessary to switch one device out of n devices operating as an online system to a spare device for the purpose of maintenance or the like.

This switching is performed by copying the memory contents to the spare main memory device and then switching the logical connection with the processing unit. This memory copying takes a certain amount of time, but during this time the processing unit remains online. servicing must continue, and therefore the program that performs the memory copy must be executed intermittently during processing unit idle time when the programs necessary to perform the online service are not running.

Furthermore, since the main memory device during memory copying also stores programs and data for executing online services, it can be said that memory copying is in progress in response to a memory access request from the processing unit. They all need to respond normally, and if they don't, it will cause serious confusion to the entire system.

In such cases, the conventional memory copy control procedure is to copy memory from one device to another.
When copying, if the former is defined as a copy source memory device and the latter is defined as a copy destination memory device, the following explanation can be given.

(1) Logically disconnect the answer data bus of the copy destination memory device, that is, the bus that sends response information when accessed.

(This prohibits the sending of response information from the copy destination memory device to the processing device.

) (2) Match the memory device names of the copy source memory device and the copy destination memory device.

(Thus, when the processing device accesses the copy source memory device, the copy destination memory device is accessed at the same time.

) (3) Read data from address 00 of the copy source memory device, write the data again to address 00 of the copy destination memory device, increment the address, and repeat from then on until the end address of the copy source memory device.

By intermittently running a program that executes (1) to (3) above during free time on the processing device, it is possible to perform memory copying without interrupting online services. As mentioned above, during memory copying, access requests are issued to multiple main memory devices at the same time.

As for memory busy management when there are requests for access to a plurality of main memory devices at the same time, if the speeds of the plurality of main memory devices are the same, the above-mentioned busy management method has no problems.

However, the aforementioned memory
When copying, the busy period differs between multiple main memory devices that are accessed at the same time. This means that some devices will be prohibited and others will be prohibited, making it impossible to apply the above-mentioned memory copy control method of accessing the main memory device being copied at the same time.

A conventional memory copy system will be described below with reference to the drawings.

FIG. 1 is a block diagram of an information processing system, in which MO,
Ml to M7 have cycle times of TO and T1 to T, respectively.
I, at least one of which is a main memory device with a different cyclotime from the others.

CC is the central control unit, MAR is the memory address bus, M
DB is a memory data bus, and MWB is a memory answer bus.

It is shown that a plurality of main memory devices MO, M1 to M7, at least one of which has a different cycle time from the others, are connected to the central control unit CC by the same bus.

FIG. 2 shows a memory busy management circuit in a conventional central control unit CC, and MTMOO to MTM70 are access request signals to the main memory devices MO to M7 in FIG.
MM70A is a flip-flop MBSYO that indicates the timing of accessing the main memory devices MO to M7 in FIG.
~MBSY7 is a slip-flop, MSYNO~M, which indicates that the main memory devices MO~M7 in FIG. 1 are busy.
SYN7 is a control line MiNH that instructs the main memory devices MO to Mγ to be released from the busy state from the central controller CC in FIG.
(~MiNH7 is another prohibition condition when accessing the main memory devices MO to M7 in FIG. 1.

Note that the "I" and rlJ of flip-flops indicate that the flip-flops operate in synchronization with the I-phase and ■-phase clocks, respectively.

Here, the clock period .tau. is divided into two, and the I-phase and ■-phase clocks are used.

FIG. 3 is a time chart of FIG. 2. When the access request signals MTMOO and MTM70 of FIG. 2 are turned on simultaneously at the timing shown in FIG. 3, the access conditions are checked, and when all are satisfied, the access timing is changed. The flip-flops MMOOA and MM70A shown are set at timing t of one phase, and the main memory devices MO and M7 are simultaneously accessed, and the in-use display flip-flops MBSYO and MBSY7 are set in the next phase (2).

Now, the cycle time of the main memory device MO is TO-5τ, M
1 cycle time T1-3τ, the busy release control line MSYNOMSYN7 from the central controller CC turns on at the timing of 5+L3, and the busy display flip-flops MBSYO and MBSY7 turn on at the next phase 1, 13, respectively. It is done in 10 minutes.

Therefore, when the next access request to the main memory device MO, M7 occurs in the ■ phase following t3, the main device M7
However, the main memory device MO is accessed only after waiting until t6, and the above-mentioned memory busy management method, which assumes simultaneous access to multiple memory devices during copying, has different speeds. It can no longer be applied between main memory devices.

The present invention eliminates such drawbacks and provides a memory busy management scheme that allows normal memory access during memory copying between main memory devices of different speeds.

That is, the present invention provides a plurality of main memory devices with different speeds,
When an access request is made to one of the main memory devices from a processing device of an information processing system including at least one processing device, a busy message from the processing device indicates that the main memory device to be accessed is not in use. On the other hand, when access requests to multiple main memory devices occur at the same time, a busy signal from the processing device is used to ensure that all of the multiple main memory devices to be accessed are not in use. It has a means for permitting access by controlling with an intermediate release control line, and enables normal memory access during memory copying between memory devices of different speeds.

The invention will be explained in detail below with reference to the drawings.

Figure 4 is the main circuit diagram of the present invention, and is
M70, MMOOA~MM70A, MBSYO~MBS
Y? , MSYNO~MSYN7 and MiNHO~MiNH
7 is the same as the same symbol in Figure 2, MABSY is M
TMOO to MBSYO, ~, is the logical sum of MTM708MBSY7.

Note that rIJ and rIJ of the flip-flops 7 indicate that the flip-flops operate in synchronization with the I-phase and ■-phase clocks, respectively.

Here, the clock period τ is divided into two, and the I-phase and ■-phase clocks are used.

FIG. 5 is a time chart of FIG. 4. When the access request signals MTMOO and MTM70 of FIG. 4 are turned on simultaneously at the timing shown in FIG. 5, the access conditions are checked, and when all are satisfied, the access timing is changed. The flip-flops MMOOA and MM7OA shown in FIG. 1 are set at timing 1 of the I phase, and the main memory devices MO and M7 are simultaneously accessed, and in the next H phase, the in-use display flip-flops MBSYO and MBSY7 are turned on.

Now, the cycle time of the main memory device MO is TO-5τ, M
7 cycle time TI-3τ, the busy release control lines MSYNO, MSYN7 from the central controller CC
are turned on at the timing of 1, 1, , respectively, and the busy display flip-flops MBSYO and MBSY7 are reset at the next {circle around (2)} phase of j5+j3, respectively.

Now, next access request MT to main memo J device MO, M7
When MOO, MTM70 occurs in the ■ phase following t3, the flip-flop MBSY indicates that the main memory device M7 is in use.
7 has already been reset, but the in-use table of the main memory device MO and the frisonoflop MBSYO have not yet been reset.
Since the access request signal MTMOO of the main memory device MO and the in-use indication flip-flop MBSYO are
The logical condition MTMOO/MBSYO is t4A between
Established in timing.

Therefore, MTMOO△MBSYO, ~, M to MTM70
MABSY, which is the logic phase of BSY7, becomes logic I11 at timing t4, and the main memory devices MO, ~, M
All memory accesses of 7 are prohibited.

This state will continue until the in-use display flag MBSYO of the main memory device MO is reset at the next phase 2 after t5, and the next access to the main memory devices MO and M7 will be allowed only at the timing of t6. Main memory device M
O and M7 are accessed simultaneously.

Therefore, the above-described memory busy management method, which is based on simultaneous access to multiple memory devices during copying, can be applied to main memory devices having different speeds.

In the circuit shown in FIG. 4, if only one access request MTMOO to MTM70 to the main memory devices MO to M7 is turned on at the same time, the in-use display node flop MBSYO of the main memory device MO to M7 to be accessed is turned on.
~ Confirm that MBSY7 is off and the next access is permitted.

As explained above, according to the present invention, it is possible to simultaneously access multiple main memory devices with different speeds.
The conventional memory copy method can be applied even between main memory devices having different speeds.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an information processing system, FIG. 2 is a memory busy management circuit diagram in a conventional central controller CC, FIG. 3 is a time chart thereof, and FIG. 4 is a block diagram of a conventional central controller CC. This is a related memory busy management circuit diagram, and the fifth
The figure is the time chart. MO, M1 to M7...Main memory device, CC...
... Central control unit, MAR ... Memory address bus, MDB ... Memory data bus.

Claims (1)

[Claims] 1. In an information processing system that includes a plurality of main memory devices with different speeds and at least one processing device and simultaneously accesses the plurality of memory devices during copying, when an access request is made from the processing device to one of the main memory devices. When this occurs, access is permitted by controlling that the main memory device to be accessed is not in use using a busy release control line from the processing unit, while requests for access to multiple main memory devices occur simultaneously. The present invention includes means for permitting access by controlling that all of the plurality of main memory devices to be accessed are not in use by a busy release control line from the processing unit, and for memory copying between memory devices of different speeds. A memory busy management method that enables normal memory access.