JPH04116732A - Timer control system - Google Patents

Abstract

PURPOSE:To shorten the copy time of timer information and to speedily switch processors by permitting MM crossing parts to monitor and transfer the update of data by means of a timer subtraction control part or the processors so as to always make the contents of the timers in both systems coincident with each other. CONSTITUTION:Time is subtracted as against the setting and starting of plural time out time generated at every process on respective processors 10 and 11. Thus, the elapse of time-out time is noticed from timer parts 105 and 115 to the processors 10 and 11. Then, all or a part of control information in the timer part in the standby system processor is made to coincide with information on the timer part of the operation system processor. Thus, the update of the data by the timer parts 105 and 115 or the processors 10 and 11 is monitored and transferred in the main memory crossing parts 103 and 113 and the contents of the timers in both systems are always made coincident with each other. Thus, the copy time of timer information can be shortened at the time of switching the processors 10 and 11 and the processors can speedily be switched.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control method for a hardware timer in a processor system using a duplex configuration.

[Prior Art] Conventionally, processor systems using a duplex configuration have maintained high reliability by always matching the memory contents of both systems, and by switching to the other processor when one processor fails. Ta.

FIG. 6 is a block diagram of a conventional dual-configuration processor system.

Each of the duplexed processors (CPU) 10.11 has a central control unit (~4PU) 101.1 that controls the whole.
111, main memory (MM) 604, 614 that holds programs and data executed by the central control unit 10.11
, a timer unit (TMG), 605.615, and a bus crossover circuit (BXC) 102 for coupling the buses of both systems. l
The city is equipped with 12. Here, the processor 10 is an active system, and the processor 11 is a standby system.

The timer sections 605 and 615 include timer management tables (TST) 6052 and 6152 for managing timer vacancies and occupancies, and a timer time holding table (TST) for holding the current remaining timer time.
DT) 6053, 6153, timeout queue (TO
Q) TMG control unit (TMC) that counts 6054, 6154 and time and controls timer units 605 and 615.
) 6051 and 6151 are provided.

The timer management tables 6052 and 6152 manage the status of the timer as unused/in use/updating/timeout.

Next, the overall operation in FIG. 6 will be described.

(1) First, the processor l○ secures an unused timer from the timer group 605. This is from processor 10 to TMG
This is done by issuing a timer reservation request to the control unit 6051. The TMG control unit 6051 searches for a timer in the timer management table 6052, notifies the timer number (TID) of an unused timer, and changes the state of the timer to in use.

(2) Next, the processor 10 sets an arbitrary timeout time in the timer. The timeout time is set by writing the set time from the processor 10 to the timer time holding table (TDT) 6053 of the timer specified by the timer number TID.

(2) Next, the processor 10 instructs to start the timer. To start the timer, the processor 10 sends a timer number (TI
This can be done by writing the set time into the timer time holding table 6053 of the timer specified in D).

The 0947 unit 605 updates the timer time independently of the processor 10. To update the timer, the TMG control unit 6051 reads the timer management table (TST) 6052 for all timers, and if the timer time is being updated, updates the timer to a value obtained by subtracting 1 from the value in the timer time holding table (TDT) 6053. If the updated value of the timer time holding table 6053 is O, it means a timeout, and the timeout is set in the timer management table (TST) 6052, and the timeout queue (TOQ) is set.
) 6054, the timer number (TTD) of that timer is written. This series of operations is performed once for each timer update time for all timers. (2) Next, the timer section 605 notifies the processor 10 of the timeout. Timeout notification is sent to timeout queue (TOQ) 60
54 is not empty, the processor 10 is notified by an interrupt. Alternatively, the processor 10 may detect a timeout from the timer unit 605. In this case, the processor 10 can know the timeout by referring to the timeout queue (TOQ) 6054.

■Finally, release the timer when it is no longer used. The timer is released by the TMG control unit (TMC) 6051 or the processor 10 setting the timer management table (TST) 6052 of the timer number (TID) to an unused state.

The above operation is executed only by the active processor 10. As a result, during operation, the contents of the timer management table (TST), timer time table (TDT), and timeout queue (TOQ) of the active processor 10 and the backup processor 11 become inconsistent, and when switching systems, the contents of the backup processor 10 and the backup processor 11 become inconsistent. In order to update the timer values, the timer management table (TST), timer time keeping table (TDT), and timeout queue (TOQ) of the active processor are transferred via the bus cross circuit (BXC), and the timer of the backup system is updated. Management table (TST), timer time table (TDT), timeout queue (TOQ)
I copied it to , and then switched the processor to 10.11.

For dual processor systems, for example,
“Electronic Communication Handbook! March 30, 1978 Co., Ltd.
Published by Ohmsha, pp. 1420-1422.

[The problem that the invention attempts to solve]

As described above, conventionally, in a fault-tolerant system, the contents of both systems are made consistent by duplication of component devices, and when a failure occurs, the system is switched from the active system to the standby system to perform uninterrupted operation 24 hours a day. In that case, as described above, at the time of switching, it is necessary to copy the information in the timer unit (TMG) to the other system. As a result, there was a problem in that the switching time increased. In particular, as the number of timers increases, the switching time increases significantly.

The purpose of the present invention is to solve such conventional problems and to
An object of the present invention is to provide a timer control method capable of quickly switching processors by shortening timer information copying time.

[Means for Solving the Problem] In order to achieve the above object, the timer control method of the present invention has the following features:
(b) An information transfer device is provided to interconnect the main memories of each duplexed processor, and a management table for managing at least one or more timers on the main memory, and a timer time holding table for holding the current time of the timer. and place a timeout queue to hold the timer number that has timed out,
The timer control device subtracts the time in the timer time holding table, updates the timer management table and timeout queue, and updates the timer management table and timeout queue in response to a timer use request activation generated by each process from the central processing unit. , is characterized in that when the timer management table, timer time holding table, and timeout queue of the timer control device are updated, the updated contents are transferred to each other via a transfer device. (b) The timer management table, timer time holding table, and timeout queue are placed in the memory under the timer control device, and a transfer device is provided to interconnect each timer control device of the duplex processor, and the transfer Another feature is that updated contents of the memory are transferred between the timer control devices of both systems via the device.

[Operation] In the present invention, the timer unit notifies the processor of the passage of the timeout time by subtracting the time for setting and starting multiple timeout times that occur for each process on each processor. At the same time, all or part of the control information of the timer section of the standby processor is made to match the information of the timer section of the active processor.

To this end, data updates by the timer section or the processor are monitored and transferred by the main memory intersection section (MMC), so that the contents of the timers in both systems always match.

As a result, when switching processors, timer information copying time is shortened, and processors can be quickly switched. Note that a timer information matching control section is provided to interconnect the timer sections of both systems, and updates by the timer section or the processor are transferred to each other via the timer information matching control section, so that the timer sections of both systems can be connected to each other. It is also possible to match the contents.

[Example] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a timer configuration diagram in a duplex system showing a first embodiment of the present invention, and shows a case where a main memory cross section (MXC) is used.

In FIG. 1, processors 10 and 11 are central controllers 101 and 111, and main memories (MM) 104 and 1, respectively.
14, MM intersection sections (MXC) 103 and 113 that perform consistency control of the contents of the main memory section (MM), and a timer section (TM
G) Equipped with 105 and 115.

The timer units (TMG) 105 and 115 are connected to the main memory unit (MM
) 104, 1.14 PT start holding register (PTHR) 1052.1152 that holds the address of the start number of the pointer table (PT) that holds the data configuration information in 1.14.
and a timer subtraction control unit (TMC) 1051.1151 that subtracts the timer in the main memory (MM).

In the present invention, the timer management table (TST) and timer time keeping table (TDT), which were conventionally provided in the timer section,
, and a timeout queue (T OQ) are both provided in main memories (MM) 104 and 114. Therefore,
The timer units 105 and 115 have a simple configuration consisting only of a control unit that subtracts the start address of the pointer table and the timer.

FIG. 2 is a data configuration diagram in the main memory (MM) in FIG. 1.

The main memory (MM) stores a timer management table (TST) that manages timer availability, a timer time holding table (TDT) that stores the current remaining timer time, and a timer number that has timed out (TID). TID to hold during timeout
A holding area (TOQ) is stored. Furthermore, T.S.
BTST/ETST, TDT (timer time holding table) that holds the upper/lower limit addresses of the T (timer management table) area
BTDT/ET that holds the upper/lower limit address of the area
BTOQ/ETO,Q that holds the upper/lower limit addresses of the DT, TOQ (TID holding area during timeout) area
, a TOQ head pointer (QHP) indicating the beginning and end of the TOQ (TID holding area during timeout), and a TOQ end pointer (QTP). BTST/ETST, BTDT/
Each address of ETDT, BTOQ/ETOQ, and QHP/QTP is specified by the PT head holding register (PTHR)]052°1152 in the timer unit (TMG).

Here, addresses in the main memory (MM) are used starting from address 8000. That is, pointer table (PT
) are addresses 8000 to 8007, timer management table (TST)
are addresses 10000 to 11023, timer time holding table (T
DT) is address 20000-21023, TID holding area during timeout (TOQ) is address 30000-31023.
Each street address is used.

The MM intersection (MXCH03,l 13) constantly monitors data updates on the main memory (MM) by the timer subtraction control unit (TMC), and when a write is detected, it is transferred to the main memory 1 (MM) of the other system. is transferred to the main memory (MM) of both systems.
Data consistency control is performed between the two.

The TST (timer management table) is formed of a busy flag section (BYF), a time updating flag section (EXF), and a timeout flag section (TOF) for each timer.

As shown in TST in Figure 2, the timer with TID=O is not in use, the timer with TID=1 is being reserved, and the timer with TID=0 is not in use.
A timer with TID=2 indicates that the timer is being updated, and a timer with TID=3 indicates that the timer is in the process of timeout. The timer that is timing out starts at address 101 pointed to by QHP, and TID=3.
An example is shown in which 100 timers from the timer 200 to the timer whose TID=888 is at address 200 pointed to by QTP at the end of TOQ are in the process of timeout.

The overall operation of the dual processor system will be described below.

Note that the case where the processor 10 is an active system will be taken as an example.

(1) First, the processor 10 secures an unused timer from the timer group. The timer is secured by the processor 10 issuing a timer reservation request to the subtraction control unit (TMC) 1051 of the timer unit 105. The subtraction control unit (TMC) 1051 controls the BT of the main memory unit (MM) 104.
Search for a timer with BYF of O in TST in the address range indicated by ST to ETST (indicated by a broken line arrow), set BYF of that timer to 1, and notify the TID of that timer.

To secure the timer, the processor 10 refers to the TST and
Search for the timer whose BYF is O, find the TID, and write BYF=
This can also be implemented by setting 1. B by the subtraction control unit (TMC) 1051 and the processor 10
The update of the YF is monitored by the MM intersection (MXC) 103, and the BYF of the processor 11 is also updated via the MM intersection (MXC) 103 and 113.

(2) The processor 10 sets an arbitrary timeout time in the timer. The timeout time is set by the processor 10 by writing the set time into the TDT (the address is calculated by BTDT+TID) of the timer specified by the TID (indicated by the broken line arrow in FIG. 2). In this case as well, the operation for updating the TDT of the processor 11 is performed by the MM intersection (MXC) 103,
113.

(2) The processor 10 instructs to start the timer.

To start the timer, the TMC is in TST (the address is BTST) for the timer of TID specified by the processor 10.
+TID) is set to 1 in EXF. Note that the EXF of the processor 11 is updated via the MM intersection (MXC) 103°113.

(2) The timer unit (TMG) 105 updates the timer time independently of the processor 10. Note that updating of the timer will be explained in detail with reference to FIG.

(2) The timer unit (TMG) 105 notifies the processor 10 of the timeout. In this case, if the TOQ is not empty, the processor 10 is notified by an interrupt. or
This can also be implemented by the processor 10 detecting a timeout from the timeout TTD holding area (TOQ) 1044 of the main memory (MM) 104. In this case, when the processor 10 refers to the TOQ,
You can know the timeout.

(2) The processor 10 releases the timer that has finished being used. The timer is released by the timer subtraction control unit (TMC) 10
51 or processor 10 with its TID (address is B
(calculated by TST + TID) BYF = ○, EXF = O, T
This is done by setting OF=O. In addition, regarding the processor 11, the MM intersection (MXC) 103. l
The update is carried out via 13.

FIG. 3 is a flowchart of the timer update process shown in FIG.

Timer subtraction control unit (TMC) l O5] is TID=
Regarding timer O, the first TST (address is BT
Step 301:
302), if the timer time is being updated (EXF=1), (
Step 303), TDT 1st (address is BT
DT+T ID) is updated to a value obtained by subtracting 1 (steps 304, 305 and 306). The relevant timer of the processor 11 is the MM intersection (MXC) 103
updated via.

If the updated value of TDT is O (step 307), it is a timeout, so EXF=O1TOF=1 is written to TST.
is set, the QTP of the TOQ is increased by 1, and the TID is written to the TOQ pointed to by the QTP (steps 308, 30
9). Note that the EX of the corresponding timer in the processor 11
F and TOF are also updated via the MM intersection (MXC) 103. Furthermore, the increment of QTP of the TOQ of the processor 11 by 1 and the write operation of the TID to the TOQ pointed to by the QTP are also updated via the MM intersection (MXC) 103.

Next, the TID is increased by 1 and the exact same operation is performed again (steps 310, 311).

This series of operations is performed once for each timer update time for all timers.

The above are the details of the timer update process.

Note that the coincidence control of information in the timer section (TMG) 105 is performed when the MM intersection section (MXC) 103 writes to the main memory section (MM) 104 of the processor 10 system. ) 114, the timer section (TMC;) 105 is written at the time of switching.
．． 115, no special processing is performed.

In addition, in this embodiment, all the information in the timer unit (TMG) is made to match between the backup system and the active system, but within the range that the switching time allows, only a part of the information is made to match, and the remaining information is There is also a method of copying information when switching.

FIG. 5 is a diagram showing the internal configuration of a processor showing a modification of FIG. 1.

In the embodiment shown in FIG. 1, the main memory (MM) is connected to the processor bus.
) and the timer section (TMG), but as shown in FIG. 5, by providing a separate memory bus, the input/output device (10) 1053 connects the main memory section (
It is also possible to connect the timer section (MM) and the timer section (TMG) to the memory bus separately. With this method, the influence of the timer section (TMG) on the usage rate of the processor bus can be alleviated. The processing of the timer section (TMG) is all the same.

FIG. 5 is a configuration diagram of a dual system processor showing a second embodiment of the present invention.

FIG. 5 shows a processor system with a duplex configuration having a timer-dedicated crossing section (TXC). Here, timer information (PT, TST, TDT.

TOQ) is provided exclusively in the timer section (TMG).

That is, main memory units (MM) 504, 514 and MM intersection units (MXC) 103, 113 are connected to the processor bus, and timer units (TRG) 505, 515 are connected.

The timer sections (TMG) 505 and 515 include PT (pointer tables) 5052 and 5152, TST (timer management tables) 5053 and 5153, and timer time holding tables (TDT).
) 5054, 5154, TID holding area during timeout (TOQ) 5055, 5155, subtraction control unit (TMC)
5051,5], 51, PT start holding register (PTH
R) 5056, 5156, and timer information coincidence control units (TXC) 5057, 5157.

The operation is the same as that shown in FIG. 1, but the timer information matching control unit (TXC) 5057.
Since the timer 157 is provided exclusively for the timer, high-speed operation is possible as a dedicated timer without using it for other purposes. The specific operation can be explained by replacing the MM intersection section (MXC) in FIG. 1 with a timer information matching control section (TXC).

In Figure 5, since the timer information is dedicated to the timer section (TMG), there is no need to use the processor bus and memory bus when updating the timer, making it possible to improve the performance of the processor and timer. be.

The timer configurations shown in FIGS. 4 and 5 can be used efficiently by selecting and using each according to the field of application.

[Effects of the Invention] As explained above, according to the present invention, the timer management table,
A timer time holding table, timeout cue, etc. are placed in the main memory, and data updates by the timer subtraction control unit (TMC) or processor 10 are monitored and transferred by the MM intersection unit (MXC), so that the timers of both systems are always updated. Since the contents are matched, the time required to copy timer information is shortened when switching processors, compared to conventional methods, and processors can be switched quickly. The present invention is particularly effective when the number of timers increases.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a duplex processor system showing a first embodiment of the present invention, FIG. 2 is a diagram of an example of the data structure in the main memory in FIG. 1, and FIG. 3 is a timer update process in FIG. 1. FIG. 4 is a block diagram of the inside of the processor showing a modification of FIG. 1, and FIG. 5 is a flowchart of the second embodiment of the present invention.
FIG. 6 is a block diagram of a conventional dual processor system. 10.11: Processor, 101, 111: Central control unit (MPU), 103, 113: MM intersection unit (MXC),
102, 112: Bus crossover circuit (BXC), 104, 1
14+main memory (MM), 105°115.505,5
15 Timer unit (TMG), 1041, 1141 1042, 1142 104.3, 1143 1044.1144 Area (TOQ), 10 Control unit (TMC), 1 Holding register, ]0 (10). : Pointer table (PT), TST (timer management table), timer time holding table (TDT), TID retention during timeout 51.1151: Timer subtraction 052.1152: PT start 53.1153: Input/output section - H

Claims (2)

[Claims] (1) In a timer control method for a duplex processor system each comprising a central processing unit, a main memory device, and a timer control device, an information transfer device is provided to interconnect the main memories of each of the duplex processors, and A management table for managing at least one or more timers, a timer time holding table for holding the current time of the timer, and a timeout queue for holding the timer number that has timed out are arranged on the storage device, and the timer control device In response to activation of a timer use request generated for each process from the central processing unit, the time in the timer time holding table is subtracted, the timer management table and the timeout queue are updated, and the main storage device stores the timer A timer control method characterized in that when a timer management table, a timer time holding table, and a timeout queue of a control device are updated, the updated contents are transferred to each other via the transfer device. (2) The timer management table, timer time holding table, and timeout queue are arranged in a memory under the timer control device, and a transfer device is provided to interconnect each timer control device of the duplex processor, and the transfer device 2. The timer control method according to claim 1, wherein the updated contents of the memory are transferred between the timer control devices of both systems via the timer control system.