JPS58138140A - Error detection circuit for digital signal - Google Patents

Abstract

PURPOSE:To detect the number of errors and the location of the errors at the same time in receiving a transmission data using the Reed-Solomon code especially, in a demodulator demodulating digital signals read out from a recording medium of PCM recording. CONSTITUTION:First, when syndromes S0, S1, S2, S3 obtained from reception data are latched at registers r0, r1, r2, r3 detection circuits d1, d2 discriminate whether or not the syndromes satisfy Equation, and if satisfied, i.e., errors exist, the flag is set to 1 and the control is given to the circuits of the next stage. simultaneously, converters C0, C1, C2 and C3 convert the syndromes in accordacne with Equation. As a result, if a signle error takes place, the detector d1 transmits the falg ''1'' to the circuit of the next stage and if double errors take place, the detector d2 gives the flag ''1'' to the circuit of the next stage.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a demodulator that demodulates a digital signal read from a PCM recorded recording medium.
The present invention relates to a circuit that simultaneously checks the number of errors and the location of errors when receiving transmission data using Solomon codes.

Now, the code polynomial C(x) of the received data whose code length is n
C(x)=Co-+-C, x+C2x2+=-+Cn-
1x''-' -・-・-(1), and in order to detect errors from this, syndrome 5i Si=C(α”), i=o, 1. -..., 2t-1
- Find (2). Here, α is the root of the primitive polynomial, γ is any integer, and αγ+1 is the generator polynomial g(X)g(x)
=(x-αr)(x-ar+1)-(x-(11+2
t-1) −, which is the root of (3). Here, t is the number of errors that can be corrected.

However, by simply determining the syndrome st'i, it is only possible to determine whether there is an error or not.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a digital signal error detection circuit that can simultaneously detect the number of errors and the error location when the number of errors is t or less. This is the purpose.

An embodiment of the present invention will be described in detail below with reference to the drawings.

Syndrome St s 1. (a2′g′l−(2+1)) sl
, (a”' − (2+ 1) ) 2s1 , (4)
Convert sequentially. Here, m is the degree of the primitive polynomial. Therefore, the syndrome 8i0c) after k transformations is 51(k)=(1-(2+1) in a2)ksl,
, , -, , (5) k = 0 * 1 + "'
+n1.

For each transformation of the syndrome, i.e. -0°1,...
.For every n-1, the detection formula (Δj) at that time.

j=1.2. ..., t seek.

Now, let the polynomial 〇(x) representing the error pattern be f3cx)−
e x”+e xt2+==-+ettx”・
” (7) Let tl t2 1 <j < t.

Here, It is.

That is, when there is one error, the determination is made as follows.

(1) Detection of snoring error (j,=1) k=4. After the conversion of , if the detection formula Δ1 becomes 5-(Δ,)k-0, -t, (8), it is a single error, and the error location is t.

The probability of a detection error is mainly determined by m and t, but in this case, in order to reduce the detection error, the detection formula % formula % (9) (Detection of 10 multiple errors (2 x t) k = t1.t2 ..., after converting tj, the detection formula Δ" becomes (Δj)k=0.-t4.t2....., t"
. . . If αO, then j is controlled, and the error locations are tl, t2. In this case, the other detection formula Δ is (a) If J<j, (ΔJ)k-0, must be -0,■,...,n-1... (
It becomes lυ.

(b) When J>j, if m is sufficiently large (ΔJX'
jO* k""0 + 1 +"'r n 1 ・
...(+216-).

As described above, by converting the syndrome shown in equation (5) and performing the calculation in equation (6), the number of errors and the error location can be detected.

This fact has been confirmed by calculations using the city's 1 child computer.

Next, the main parts of the tl error detection apparatus based on the above method will be explained with reference to the block diagram shown in FIG. In this figure, Dl, D2. ..., D, is l, 2. . . , are detectors that detect multiple errors, respectively.

The circuits and operations of the main parts of the device d will be explained in detail.

For the sake of simplicity, the double error detection circuit will now be described with reference to the block diagram shown in FIG. Here it is.

Here, the primitive polynomial p(X) is defined as p(x)=1−)x +x +x +x
-f131.

Therefore, if m = 8 and the root of the primitive polynomial p(x) is α, this is the primitive light of the Galois field GF(2), and becomes a circle. Moreover, when syndrome 5ik) is expressed as a polynomial, s'tk)-s (k)<x)-β. +β, x1−/2
x2. -00. +β7x798. (19. Here, β0 is the LSB and β7 is the MSB.

If we define the primitive polynomial p(x) and its root α in this way, we get
The conversion formula for syndrome 81 is based on formula (5).

In addition, if the detection formula Δ is j = 1 (single-error detection), determine whether it is (i.e., S packing) -8% k) ...... (18), and then = 2 (double error detection), whether (S5k) 10s (i k ) ) (s5) 15
ik))-(S(k)十S躬))2... (20)
It will be determined whether or not.

9- Next, details of each part in FIG. 2 will be explained.

Conversion formulas (16a), (16b), (
The conversion circuit for (16c) and (16d) is shown in Figure 3(a).
), (b), (e) and (d).

Here, the logical symbol of r-t with X3 and X4 numbered is:
rnod 2 addition of all inputs, i.e. (βi+β
j + βk) mod 2 -... (2]) and (βi + βj + β + βz) mod 2 ...
...Represents (a). The same applies to other circuit diagrams.

Regarding the detection circuit, since a single error detection circuit can be easily constructed using an 8-bit magnitude comparator, an example of a double error detection circuit is shown in FIG.

Here, the logical symbol numbered t represents the exclusive OR of the corresponding bits of the two syndromes 5fk) and 85k). That is, ((Sj”)t+(Sjk))tl rnod 2
, l=o, ■, -, 7... (a) Represents 10-. The circuit numbered β2 is a multiplier circuit for two arbitrary elements of the Galois field GF (28), and an example of this multiplier circuit is shown in FIG.

In this circuit (S51υ+5(k)) (S(k)10S)...
... - is calculated.

The circuit numbered β3 is a squaring circuit for any element of the Galois field GF(28), and an example of this squaring circuit is shown in FIG.

In this circuit (S(k) 15(k))2 ・・・・・・・・・
(c) is calculated.

The circuit numbered β4 is a circuit that compares any two elements of the Galois field GF(28), and is 8-bit.

It is sufficient to use a magnitude detector of

In this circuit, (s(k) 15F)) (S5k) 15r)) = (SF)
+55k))2...Determine whether it becomes @.

The multiplication circuit shown in FIG. 5 will be explained.

The logical symbol numbered with g is all the bits of some element
represents the exclusive OR of two bits. That is, (β1+rj) mod2 t==011 +...,
7 ”・Represents @.

The circuits numbered j11+...+ & 6+a7 are the circuits that multiply α,..., α, α, respectively, and these are shown in Figures 7(,) to 7(g). .

The logic symbol numbered m is a circuit that adds arbitrary eight elements X, (i=1, 2, . . . , 8) of the Galois field GF (28). That is, r of the corresponding 8 bits
With lod2 addition, (Σ(Xt)j) mod 2, j=o, 1. -, t
Represents H-1.

Next, the operation of this apparatus will be explained with reference to FIG. First, syndrome S is determined from received data. , s
l, s2. s3 is register r. , rl.

When latched to r2+r3, the detection circuit d7. It is determined whether d2 satisfies each expression (Fun2 formula GO) 't-, and if it is satisfied, that is, if there is an error, for example, a flag is set to 1 and sent to the next stage circuit. Also, at the same time, converters C6,C,, C2,C, express these syndromes by equations (16m), (,16b), and (16c), respectively.

(16d). Each syndrome converted by the next clock is stored in register r. + r
1+r2* latched to r5, detection circuit d,.

C2 and conversion circuit C8r e1+ e2+ C5 repeat the operations described above. Thereafter, this process is repeated n times (n: code length) including the first syndrome latch.

As a result, if a single error occurs at the position t, the detector d sends a flag 1°' to the next circuit after converting t, indicating that a double error has occurred at the position 11.12. If so, the detector d2 sends the flag l" to the next stage circuit after the 14,12 conversion, and in this way detects whether it is a single error or a double error, and simultaneously detects the 13-error location blindness. I will do it.

In the demodulator, the magnitude of the error is determined based on this detection result and correction is performed.

[Brief explanation of drawings]

Figures 1 to 7 are diagrams showing one embodiment of the present invention.
The figure is a diagram showing the main parts of the multiple error detection device, Figure 2 is a block diagram showing the double error detection circuit, and Figure 3 (
) to (d) are block diagrams showing conversion circuits, Fig. 4 is a block diagram showing an example of a double error detection circuit, Fig. 5 is a Zorock diagram showing an example of a multiplication circuit, and Fig. 6 is a block diagram showing an example of a double error detection circuit. A block diagram showing an example, Fig. 7 (&) to (g) is α...
- It is a block diagram showing a circuit that multiplies C6 and C7, respectively. To+ r1+ r2+ r5...Register\CoIC
11C2-c3...Converter, d, C2...Detector. Applicant's representative Patent attorney Takehiko Suzue 14- Figure 7 (9) Showa year, month, day, Japan Patent Office Commissioner Shima 1) Haruki Tono1, Indication of case Patent application No. 57-207962, Title of invention Digital signal Error detection circuit 3, relationship with the case of the person making the amendment Patent applicant (240) Sansui Denki Co., Ltd. 4, agent 6, specification to be amended 7, contents of the amendment (11 claims as attached) (2) In the 10th line of page 3 of the specification, it is corrected to read "to detect" instead of "to lateral to". 2. Scope of Claims (1) Generator polynomial: (g(x )) g(x)−(x a?) ('x a”)=(x
-a""") Here, the transmission polynomial of the Reed-Solomon code generated by the root 1 of the primitive polynomial of order α-m = arbitrary integer t = error correctable number: [:C(X)) C(x ) −Co+Cr Here, a first means for latching the plate = O, l, ..., (21-]), and a syndrome S, (
0), (0), ('ri trr, -(t
+ i )S+ -+8+ (α)(
=Si"')→...→S plate (0)(αtrTL-("
'))k(-8t(k))→,,. Here = o, 1. . . . , (n-+), and a second means for sequentially converting the syndrome S, (k).'
14. A digital signal error detection circuit, characterized in that the circuit is characterized in that it simultaneously detects the number and location of errors. (2) For single-error detection (Δ1) S in addition to the operation of k. The error detection circuit according to claim 1, wherein the error detection circuit makes a determination as follows: (k) -8, (kl-...=82).

Claims (2)

[Claims] (1) Generator polynomial: [g(x) ) g(x)=(x-αr)(x-αγ+1)...(X-
α7”+2t-1) where α = root of m-th order primitive polynomial γ = arbitrary integer t - transmission polynomial of Reed-Solomon code generated by error-correctable number: (C(X) ) C(X) =C0+C1X+C2X2+...Cn
In a demodulator that receives and demodulates a digital signal injected with -1 A first means for latching (2t-1), and a syndrome s latched by the first means =
(o) as B1(o'), B, (a2m-(2+1))(=81(
'))Uh,,,0. . −41((12m ”1))k(=Si(k))−+,
-1,. Here, a second means for sequentially converting =0, 1, ..., (, -1) and a third means for calculating for each conversion of the syndrome 51(k) are provided. A digital signal error detection circuit characterized by simultaneously detecting the number and location of. (2) In the case of single-error detection, the addition (3(k)-B(k)=,...-8Sk2.0 size B) is performed on the calculation of (Δ,)k. In claim 1, '
Error detection circuit on nl'i.