JPS5813774U - Image information density determination circuit for facsimile equipment - Google Patents
Image information density determination circuit for facsimile equipmentInfo
- Publication number
- JPS5813774U JPS5813774U JP10612781U JP10612781U JPS5813774U JP S5813774 U JPS5813774 U JP S5813774U JP 10612781 U JP10612781 U JP 10612781U JP 10612781 U JP10612781 U JP 10612781U JP S5813774 U JPS5813774 U JP S5813774U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- image information
- information density
- determination circuit
- density determination
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Facsimile Scanning Arrangements (AREA)
- Facsimile Image Signal Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案による画情報密度判定回路の概略構成を
示すブロック図、第２図はその動作を説明するための要
部の波形図、第３図は第１因の第２回路の設定時間につ
いて説明するための図である。
１・・・・・・第１の回路、２，３・・・・・・第２の
回路、６゜７・・・・・・第３の回路。Fig. 1 is a block diagram showing the schematic configuration of the image information density determination circuit according to the present invention, Fig. 2 is a waveform diagram of the main part to explain its operation, and Fig. 3 is the setting of the second circuit which is the first factor. FIG. 3 is a diagram for explaining time. 1...First circuit, 2,3...Second circuit, 6°7...Third circuit.
Claims (2)
の第１の回路の出力によりトリガされ上記画信号の１ラ
イン期間よりも充分小なる一定時間を設定する第２の回
路と、この第２の回路の設定時間内に次の変化点が到来
するか否かを検出する第３の回路を備え、この第３の回
路の出力を得て画情報密度を判定するようにしたファク
シミリ装置の画情報密度判定回路。(1) A first circuit that detects a change point in a binary image signal, and a second circuit that is triggered by the output of this first circuit and sets a certain period of time that is sufficiently smaller than one line period of the image signal. and a third circuit for detecting whether or not the next change point arrives within the set time of the second circuit, and the image information density is determined based on the output of the third circuit. Image information density determination circuit for facsimile machines.
密度をＮ１上記画信号を得るための１ライン分の走査期
間をＴ、 １ライン分の走査距離をＤとして、Ｔ／ＤＮ
に選定されることを特徴とする実用新案登録請求の範囲
第１項記載の画情報密度判定回路。(2) The setting time of the second circuit is T/DN, where the image information density to be detected is N1, the scanning period for one line to obtain the above image signal is T, and the scanning distance for one line is D.
An image information density determination circuit according to claim 1, which is selected as a utility model.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10612781U JPS5813774U (en) | 1981-07-16 | 1981-07-16 | Image information density determination circuit for facsimile equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10612781U JPS5813774U (en) | 1981-07-16 | 1981-07-16 | Image information density determination circuit for facsimile equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5813774U true JPS5813774U (en) | 1983-01-28 |
Family
ID=29900637
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10612781U Pending JPS5813774U (en) | 1981-07-16 | 1981-07-16 | Image information density determination circuit for facsimile equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5813774U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63120966U (en) * | 1987-02-02 | 1988-08-05 |
-
1981
- 1981-07-16 JP JP10612781U patent/JPS5813774U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63120966U (en) * | 1987-02-02 | 1988-08-05 |
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