JPS63121965U

JPS63121965U -

Info

Publication number: JPS63121965U
Application number: JP1341987U
Authority: JP
Priority date: 1987-01-31
Filing date: 1987-01-31
Publication date: 1988-08-08

Description

[Brief explanation of the drawing]

第１図は本考案によるマーク検出回路の一実施
例を示すブロツク構成図である。６……読取画信号、７……画信号同期クロツク
、８……マーク検出区間信号、９……マーク検出
信号、１０……マーク検出回路リセツト信号、１
１……リードオンリーメモリ、１２……カウンタ
、１３……カウンタ、１４……インバータ回路、
１５……アンド回路。第２図は本考案における原稿走査面を示した図
である。１……読取主走査方向、２……読取副走査方向
、３……読取走査範囲、４……マーク検出区間（
主走査方向）、５……原稿読取区間（主走査方向
）、ａ……マーク。第３図は本考案によるマーク検出回路の入力信
号を示した図である。７……画信号同期クロツク、６……読取画信号
、８……マーク検出区間信号、１９……マーク検
出区間画信号、２０……原稿読取区間画信号、２
１……主走査１ライン周期。第４図は本考案によるマーク検出回路のリード
オンリメモリの書込内容とマークとの比較とを表
示した図である。２２……主走査方向、２３……副走査方向、２
４……マーク、２５……マーク検出区間。第５図は本考案以前に考案された飛越走査スキ
ヤナの飛越マークの検出方法を説明するための図
である。５１……読取主走査方向、５２……読取副走査
方向、５３……読取走査範囲、５４……マーク検
出区間（主走査方向）、５５……原稿読取区間（
主走査方向）、５６……飛越マーク、５７……原
稿読取区間（副走査方向）、５８……原稿読飛ば
し区間（副走査方向）、５９……飛越マーク検出
時の主走査１ラインの画信号、６０……飛越マー
ク未検出時の主走査１ラインの画信号、６１……
飛越マーク信号、６２……画信号。 FIG. 1 is a block diagram showing an embodiment of a mark detection circuit according to the present invention. 6... Read image signal, 7... Image signal synchronization clock, 8... Mark detection interval signal, 9... Mark detection signal, 10... Mark detection circuit reset signal, 1
1...Read-only memory, 12...Counter, 13...Counter, 14...Inverter circuit,
15...AND circuit. FIG. 2 is a diagram showing a document scanning surface according to the present invention. 1...Reading main scanning direction, 2...Reading sub-scanning direction, 3...Reading scanning range, 4...Mark detection section (
main scanning direction), 5... document reading section (main scanning direction), a... mark. FIG. 3 is a diagram showing input signals of the mark detection circuit according to the present invention. 7... Image signal synchronization clock, 6... Reading image signal, 8... Mark detection section signal, 19... Mark detection section picture signal, 20... Original reading section picture signal, 2
1...Main scanning 1 line period. FIG. 4 is a diagram showing a comparison between the contents written in the read-only memory of the mark detection circuit according to the present invention and the marks. 22...Main scanning direction, 23...Sub scanning direction, 2
4... Mark, 25... Mark detection section. FIG. 5 is a diagram for explaining a method of detecting interlaced marks in an interlaced scanner devised before the present invention. 51...Reading main scanning direction, 52...Reading sub-scanning direction, 53...Reading scanning range, 54...Mark detection section (main scanning direction), 55...Document reading section (
(main scanning direction), 56... skipped mark, 57... document reading section (sub-scanning direction), 58... document skipping section (sub-scanning direction), 59... image of 1 line in main scanning when detecting skipped mark Signal, 60... Image signal of 1 line of main scanning when skipped mark is not detected, 61...
Jump mark signal, 62...Picture signal.

Claims

[Scope of utility model registration request]

A certain section of the main scanning line in the scanning screen is defined as a mark detection section, and in a scanner device that has a function of detecting marks within the mark detection section during sub-scanning operation, the mark detection section of one main scanning line that has been read is used. Measure the width of the mark, compare it with the mark shape data stored in the mark detection circuit, and determine whether the total number of bits of the mark read in multiple lines consecutively is within the length of the mark in the sub-scanning direction. A scanner mark detection circuit is characterized in that it determines whether a mark is detected or not by detecting a proper number of marks.