JPS58137382A - Digital color encoder - Google Patents

Abstract

PURPOSE:To decrease an operation speed by supplying color signals to matrix circuits, low-pass filters, and delay circuits after lowering a data rate. CONSTITUTION:Color signals from latch circuits 4-6 are supplied to matrix circuits 12 and 13; an Y signal outputted from the matrix circuit 12 is supplied to an Y/C mixer 22 through a delay circuit 16 and an I signal outputted from the matrix circuit 13 is supplied to the Y/C mixer 22 through a low-pass filter 17 and a digital modulating circuit 20. Similarly, latch circuits 7-9 and matrix circuits 14 and 15 generate an Y and a Q signal, which are modulated by a delay circuit 18, low-pass filter 19, and digital modulating circuit 21 to send the resulting signal to an Y/C mixer 23. The outputs of the mixers 22 and 23 are selected alternately by a select pulse of frequency 4fsc (frequency of color subcarrier) and led out together with a synchronizing and a burst signal which are added by a mixer 26.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital color encoder applied to processing the output of an OOD camera, etc., and in particular reduces the speed of the processing circuit (Fig. 1), makes it possible to use Mos,
This facilitates LSI implementation.

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, red, blue, and edge digital color signals SRI and SB1 are input from each input terminal indicated by 1, 2.3.
．． SGI is supplied. These color signals SRI, SB
I, 5ti1, as shown in the first figure AK, da fsa
(fsa: color subcarrier frequency) data rate (sampling frequency).

The color signal SRI is supplied to latches 4 and 7, and the color signal SB
I is supplied to latches 5 and 8, and color signal 8G1 is supplied to latches 6 and 9.

Latches 4, 5.6 are operated by a latch pulse from terminal 10 at a frequency of fsc, and latch 7.8.9 is operated by a latch pulse from terminal 10 at a frequency of It operates using latch pulses shifted by π. From each of the latches 4 and 5.6, color signals SR1, 8B, . Also,
Although not shown, the data rate is similarly changed from the latch 7.8°9 to the nine color signals SRI, SB3, S.
G3 occurs. Since the phases of the latch pulses are made to differ by π, the color signal SRm + "B3 + 8G, and the color signal S
The phase of R, SB spirit and SG is shifted by π.

Color signals SR,, SB, from latches 4, 5.6, respectively.

Sa, is supplied to the matrix circuits 12 and 13, and Ma)
The IJ circuit 12 generates a Y (luminance) signal shown in FIG. 1 O, and the matrix circuit 13 generates one of the color difference signals shown in the same figure. This engineering signal is /j M
The signal is supplied to the digital modulation circuit 20 via a digital low-pass filter 1T with a band of H2, undergoes digital modulation of 1.1 fsa, and is converted into a color signal shown in FIG. 1E. The Y signal from the matrix circuit 12 is supplied to the Y10 mixer 22 via a delay circuit 16 for phase matching.
Y shown in Figure F is added to the above-mentioned modulated signal.
and construction number is formed.

In addition, the color signals SRm + from each of the latches 7, 8, and 9
SBI r SGI is supplied to matrix circuits 14 and 15 to form %Y and Q signals. This Ql1
The signal is limited to a band of 0.5MH7 by a low-pass filter 19, and is modulated by a digital modulation circuit 21.
Via the delay circuit 18! The signal is added to the mixer 23. From this mixer 23, Y and Q signals shown in Figure G appear. Matrix circuit 12.13,14. I
At s, Y, engineering, and q signals are formed by the following calculations.

Yi = 0.30 R1+ 0. ／ ／ Bi ＋
0. j; q et 1=O0OR1-0,,3
i −Q,, lzaGlqt = 0.2 / nt +
o,j/B1- o,s 2GtAnd mixer 220 output (Fig. λF) and mixer 23 output (second
G) are supplied to a multiplexer 24 and are alternately selected by a select pulse from a terminal 25 with a frequency of 1lfsc. Therefore, from the multiplexer 24, a signal, a Q signal, and a Y signal digitally modulated into 5-64 phases appear as shown in FIG. 2H. Further, the signal is supplied to the mixer 26, where a digital synchronization signal and a par-stop signal from the terminal 2T are added, and a digital composite color television signal is taken out at the output terminal 28.

Note that when generating an analog composite color television signal, a D/A converter is connected to the output terminal 28. The D/A converter may be connected to the outputs of the mixers 22 and 23, in which case the D/A converter is operated with a sampling clock of 1f8a.

As can be understood from the above description of the embodiment, according to the present invention, after lowering the data rate of the lItfga color signal, ! Since the signal is supplied to a matrix circuit, a low-pass filter, a delay circuit, etc., the operating speed of these circuits can be reduced. Therefore, these circuits can be configured using 0MO8 without using KOL+TTL high-speed logic elements, and can be easily integrated into an LSI.

FIG. 3 shows another embodiment in which this generation is applied when the data rate of the input color signals SR1, SBI, and 8Gl is 3FTRA as shown in FIG. A.

In this example, the data rate is lowered to -fga by dividing the input signal into three phases. For this purpose, the color signals SRI, SBI, and SGK are supplied to latches 29, 30, and 31 each including three latches. These latches are connected to terminals 32, 33° from latch 29
As shown in FIG. 1, a color signal converted to a data rate of fsa appears. The color signal obtained from the output of this launch 29 is supplied to matrix circuits 35 and 36 8.
A Y signal and an L signal as shown in FIG. 0 and the same figure are formed.

These two signals are added by a mixer 4T via a delay circuit 41 and a low-pass filter 42 with a band of 0.3 to 2, respectively, and the Y and L signals shown in FIG. 2 are obtained from the mixer 4T.

The outputs of the other latches 30 and 31 are also connected to the IJ circuits 37, 38 and 3!, respectively. i, 40, a Y signal, an M signal, and an N signal are formed. Figure 4 1 is mixer 4
8, and G in the figure shows the output of the mixer 49.

Here, the L, M, and ml color difference signals are formed by the following calculations.

LL = Ui = -= -0,15R1+ 0.4
4Bi -0,29Gi2.03 = -0,46R1-0,13Bi + 0.59
Gi=0.60R1-0,31Bi-0,29G
It can be represented by i3 vectors. The outputs of the mixers 47, 48, 49 are then supplied to the multiplexer 50. This multiplexer 5o is operated by a 3 fsc select pulse from a terminal 51, and a signal shown in FIG. q H appears at its output. multiplexer 5
0 performs three-phase digital modulation. The synchronization signal, burst signal, etc. are added by the mixer 26, as in the previous embodiment.

In addition, input color signals having a data rate of
The data rate may be lowered to f8Q by dividing the signal into q phases. These latches 52 to 55 each have 3
terminals 56.57, 58.59
It is operated with latch pulses of 0 phase, -phase, π phase, and -phase at the frequency of f8Q supplied from . The output of the latch 52 is then supplied to a Y and signal forming circuit 60, which includes a matrix circuit, a delay circuit, a low pass filter, a modulation circuit, and a Y70 mixer similar to the previous embodiment.

The respective outputs of the other launches 53, 54, and 55 are connected to the Y and Q signal forming circuits 61. ! and a signal forming circuit 62 and a signal forming circuit 63 for Y and -Q signals.

The respective outputs of these forming circuits 60, 61, 62, 63 are combined by a multiplexer 64. multiplexer 6
4 is operated by the Qfsc select pulse from the terminal 65, and a signal similar to that shown in FIG.

According to the other embodiments of the present invention described above, it is possible to reduce the operating speed of the circuit that processes color signals, and it is possible to obtain a configuration suitable for LSI using MOi9.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
2 is a time chart used to explain the operation of one embodiment of this invention, FIG. 3 is a block diagram showing the configuration of another embodiment of this invention, and FIGS. A time chart and a vector diagram used to explain the operation of the example, and FIG. 6 are block diagrams showing the configuration of still another embodiment of the present invention. 1.2.3... Color signal input terminal, 4.
5.6゜7.8.9.29.3G, 31.52.53゜54.55... Latch, 12, 13
, 14.15° 35.36, 37.3g, 39.40・
・・・・・・Matrix circuit.

Claims (1)

[Claims] n・-ft3 (however, fsc is the color subcarrier frequency, n=ko, 3.da,... and m=/, 2.3...
The three digital color signal inputs of the natal rate (mfsc) are lowered to the data rate (mfsc) of - and divided into 1n phases, and each phase of the n phase is converted into a composite color television from the corresponding input color signal. A digital color encoder that forms a sum signal of components corresponding to a luminance signal and a carrier color signal, and synthesizes the sum signals of each phase to obtain a composite color television signal.