JPS58137188A - Ic memory with majority circuit - Google Patents

Abstract

PURPOSE:To obtain an IC memory with a majority circuit which has a high- speed operation with a simple constitution, by performing a majority process through an adder circuit, transistors connected with a common emitter, etc. CONSTITUTION:The outputs of an odd number of memory units 1 are added together through an adder circuit consisting of resistances R1 and R2 of a majority circuit 2a and then supplied to a transistor circuit connected with a common emitter of an analog switch consisting of transistors TRQ1 and Q2 connected with a common emitter, resistances R3 and R4, a constant current circuit 21a, etc. Then a majority process is performed through a comparison with the reference voltage VREF that is applied to the base of the TRQ2, and a TRQ3 produces an emitter output which works in response to the result of majority decision. In such a way, an IC memory containing a high-speed majority circuit with no delay of plural stages is obtained with a simple constitution in which a logical circuit element stage like an NAND circuit of plural stages, etc. is not used.

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention To improve an IC memory that can disguise a majority circuit for output-
0 (b) Background of the technology Information processing systems are required to perform faster logical processing, and the probability that the information processing system will operate normally within a predetermined execution time without interrupting its operation is high. In other words, it is desired to make the height of A8 as high as possible.

(e) Flaws x class techniques and supporting oil points When v-foundation occurs in the conventional information processing system, it is automatically detected and repaired within the system without the need for human intervention, so that the system does not stop or interrupt. A method using ECC processing and a majority voting circuit is known as a means for achieving this. The former requires 311 circuits to polish and repair the 114 pieces of data, and it is necessary to temporarily reduce the reading process of the VK thread data as soon as the repair operation of the erroneous 9 data is completed. On the other hand, the majority circuit is a logic circuit of three or more odd-numbered sets.
Thus, more than a thousand judgment signals are obtained. Even if something goes wrong with this circuit, it's still the same theory! KNAN can process without stopping the II & 8 circuits, but obtains a majority vote from 3 sets.
D4(b) has the disadvantage of a total delay of 4 stages in terms of the number of stages of logic circuit elements, and the following 0
CL can be used to create high-speed multi-order circuits using fewer circuits.
The present invention aims to provide an IC memory equipped with a processing output means.

(・) The structure of the invention and its purpose is to provide an IC mail of at least 3 envy or more that performs parallel works in the same package in a collection m1ld path constituted by the first order of numbers according to the present invention. The output signal is inputted to an analog switch using a common circuit transistor (ECL) having a parallel circuit and compared with a reference voltage to determine the majority value of the input signal. It is possible to read the corpse.

(f) Example of the invention The following is an example of the invention with reference to the screen.
I will clarify.

Figure 2-(2) is a circuit diagram of the majority circuit versus IC voltage level in an embodiment of the present invention, 2M) is a circuit diagram of the circuit Mk & i in the majority circuit, and a diagram of the voltage level of the circuit 3.
Ru.

In the figure, No. 1 Gomeseri unit number 1-3, 2aV:i
With majority circuit 21a is 5E turtle flow 1 path, Ql, 2.
3 is a transistor, and R1, 2, 3, and 4 are resistors.

The memory unit 1 is the same as the conventional ECL thread memory unit, and an additional 31 circuit consisting of resistors R1, 2 is inputted to an ECL circuit consisting of a transistor Q1.2, resistors R3, 4, and a constant voltage sinking circuit 21m. Transistor Q3 is an output buffer circuit and also serves as a Schillepel transform. 0ECL is a current switch and two transistors Ql, 2.
The input side transistor Q1 is connected to the input side transistor Q1.
The transistors Q1 . V to either transistor of Q2
It operates so that the L flow flows. Therefore memory unit 1
A signal is input to the ECL from 31. Memory: Output of Lnit 1'@h resistor R1@2 by Ishiku, Mai [
Due to G'l omission, Anagasugu is added and 1ik1 of 4 hours is added.
When the input signal VINO~4 indicating 1 is applied to the base of 91, ECL, which is transistor Q1.2, is next! The input signal vINO~3 is set to J as shown in
It compares it with rEp and outputs a signal to the collector of the transistor Ql, that is, the output terminal of the transistor Q3.

Table Input signal ■IN・~4 and output signal VREF are vXNl and ■I)J as shown in Figure 3.
Set a value Kl) equal to the intermediate level of 2. Therefore, not only in VINO and vXNl where memory unit 1 normally creates all 31 signals and obtains a complete signal, but also in vrNl and VIN2 where 1 & error among 31 occurs, normal tB force due to majority decision jI'l1wFK is obtained. It can be used as an output signal. The above 1 duck is 3 gauze multi-side I wokai road 2a
It goes without saying that a majority circuit can be constructed by setting the majority reference level VREF in the same manner for three or more odd-numbered sets.

-) As described in detail, according to the present invention, the majority circuit is not constructed by the conventional combination of NANDs as shown in Fig. 1.) The majority circuit is obtained by a small number of circuit configurations, so signal processing with high-speed operation is possible. Furthermore, since the majority circuit is included in the same package, the reliability of the information processing system can be improved without changing the external circuitry.

[Brief explanation of drawings]

Iris 1- is a block diagram of a conventional IC memory with a majority circuit, FIG. Atsushiji Yui - Diagram, No. 31
is the voltage level in the majority circuit. Substitute and Hanado Hiroshi Matsuoka 18I Town Price 1 Figure 2 Figure 3

Claims (1)

[Claims] In an integrated circuit composed of an odd number of circular elements, at least an odd number greater than or equal to st, which operate in parallel within the same package! A 1lIc memory is installed, and the t output signal is input to an ablog switch using a common emitter contact transistor (ECL) having an adder circuit, and compared with a reference voltage for determining the majority of input values.