JPS58134A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58134A JPS58134A JP9939281A JP9939281A JPS58134A JP S58134 A JPS58134 A JP S58134A JP 9939281 A JP9939281 A JP 9939281A JP 9939281 A JP9939281 A JP 9939281A JP S58134 A JPS58134 A JP S58134A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- frame
- semiconductor device
- lead frame
- pellet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000008188 pellet Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 7
- 238000007789 sealing Methods 0.000 claims description 4
- 239000000470 constituent Substances 0.000 claims 1
- 239000011347 resin Substances 0.000 abstract description 4
- 229920005989 resin Polymers 0.000 abstract description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 3
- 238000007689 inspection Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000011265 semifinished product Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の組立及び最終検査を連続且つ自動
的に行なう方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for continuously and automatically performing assembly and final inspection of semiconductor devices.
半導体装置の組立及び最終検査は、数多くの作業の組み
合わせであるが、従来これらの作業は、各作業単位毎Ｉ
ζ行なわれていたため、各作業単位間の半製品の取扱い
に多くの人手を要し、また各作業単位毎のストック量が
増え、これらが半導体装置の原価を上げる要因となって
いた。Assembly and final inspection of semiconductor devices are a combination of many tasks, but conventionally these tasks are
ζ, it required a lot of manpower to handle the semi-finished products between each work unit, and the amount of stock for each work unit increased, which caused an increase in the cost of semiconductor devices.
本発明は、このような点に鎌みてなされたもので、長尺
の連続リードフレームの状態で半導体装置の組立゛及び
最終検査を行なうことにより、各作業単位毎のストック
量を無くし、且つ作業単位間に人手を全く必要としない
ものとし、連続で且つ自動的に半導体装置を完成するこ
とができる方法を提供するものである。The present invention has been made in consideration of these points, and by performing the assembly and final inspection of semiconductor devices in the state of a long continuous lead frame, it is possible to eliminate the amount of stock for each work unit and to reduce the amount of work required. The present invention provides a method that does not require any human intervention between units and can continuously and automatically complete semiconductor devices.
まず、本発明による半導体装置の製造方法の概要をｉ１
図により説明する。図において、（２）は半導体装置組
立用のリードフレームであり、供給リール（１１に巻か
れている。このリール（１１よりリードフレーム（２）
が、順次以下の組立機に供給される。。First, an overview of the method for manufacturing a semiconductor device according to the present invention will be given in i1.
This will be explained using figures. In the figure, (2) is a lead frame for semiconductor device assembly, which is wound around a supply reel (11).
is sequentially supplied to the following assembly machines. .
（３Ｊはリードフレーム（２）を連続的ｌこ送り出すフ
レ−ム送り機である。これは、スプロケット、ローラ。(3J is a frame feeder that continuously feeds the lead frame (2). This is a sprocket and a roller.
ラチェットなどと呼ばれる種々の方法のうち、これを使
用しても良い。このようにして送り出されるリードフレ
ーム（２）に対し、ダイボンダ（４）において、半導体
ペレットが鑞付される。次に、ワイヤボンダ（５）によ
り、上記半導体ペレットの電極とリードフレーム（２）
のリード間が配線される。次に、封止機（６目こより、
上記半導体ペレットの周囲が樹脂等で封止され、半導体
装置が形成される。次に、リードカッタ＋７１で、半導
体装置のリードが少なくとも１本を除いてリードフレー
ム（２）の枠から切り離される。次に、テスタ（８Ｊに
より、半導体装置の電気特性の検量がなされる。次に、
印刷機（９）により、−上記電気特性の検査結果にもと
づいて半導体装置に印刷がなされる。次に、リードカッ
タ叫により、半導体装置がリードフレーム（２］の枠か
ら完全に切り離される。残されたリードフレーム（２）
の枠は、巻取リール（１１）に巻き取られる。Among various methods called ratchets, etc., this may be used. A semiconductor pellet is brazed to the lead frame (2) sent out in this manner in a die bonder (4). Next, the wire bonder (5) connects the electrode of the semiconductor pellet to the lead frame (2).
Wiring is done between the leads. Next, the sealing machine (from the 6th point,
The periphery of the semiconductor pellet is sealed with resin or the like to form a semiconductor device. Next, the leads of the semiconductor device except for at least one lead are cut off from the frame of the lead frame (2) using a lead cutter +71. Next, the electrical characteristics of the semiconductor device are calibrated using a tester (8J).Next,
The printing machine (9) prints on the semiconductor device based on the test results of the electrical characteristics. Next, the semiconductor device is completely separated from the lead frame (2) by the lead cutter.The remaining lead frame (2)
The frame is wound onto a take-up reel (11).
以上の説明のように、半導体装置の組立及び最終検査が
間断なく行なわれ、途中のストックもなく連続で自動的
に行なわれる。As described above, assembly and final inspection of semiconductor devices are performed continuously and automatically without any intermediate stocking.
次に、第２図（ａ）〜（ｆ）を用いて本発明による製法
を具体的に説明する。Next, the manufacturing method according to the present invention will be specifically explained using FIGS. 2(a) to 2(f).
第２図（ａ）に示すように、連続する枠部０ηに一端が
保持されて半導体ペレットが固着されるリード（１６ａ
）と、上記枠部αηに一端が保持されて上記半導体ペレ
ットの電極と結線されるリード（１６ｂ）とからなる半
導体装置構成区分（ホ）を連続して設けた長尺状のリー
ドフレーム（２）を連続的に送りながら、上記リード（
１６ａ）に半導体ペレット（ｌｆｉがダイボンダ（第１
図（４））により鑞付けされ、金細線θ葎が半導体ペレ
ットα力の電極とリード（ｘ６ｂ）間にワイヤボンダ（
第１図（５））により接続される。次に、第２図（ｂ）
に示すように、樹脂Ｉにて封止機（第１図（６））によ
り封止され、半導体装置ａ〜が形成される。As shown in FIG. 2(a), a lead (16a
) and a lead (16b) whose one end is held by the frame portion αη and connected to the electrode of the semiconductor pellet (e) is a long lead frame (2). ) while continuously feeding the above lead (
16a) is attached to the semiconductor pellet (lfi is the die bonder (first
The wire bonder (Fig. (4)) is used to solder the thin gold wire θ between the electrode of the semiconductor pellet α and the lead (x6b).
(5)) in FIG. Next, Figure 2(b)
As shown in FIG. 1, the semiconductor device a is sealed with resin I using a sealing machine (FIG. 1(6)).
次に、第２図（Ｃ）に示すように、半導体装置α山のリ
ード（１６ｂ）がリードカッタ（第１図（７ｊ）を用い
て切断され、リードフレーム（２）の枠部０７１から分
離される。次゛に、第２図（ｄ）に示すように、テスタ
（第１図（８］）の電気接触子α槌が半導体装を州のリ
ード（１８ｂ）とリードフレーム（２）の枠部ａηに接
触し、半導体装置０〜の電気特性が測定される。この測
定結果にもとづいて、第２図（８）に示すように、印字
（Ｉ９）が印刷機（第１図（９））により印刷される。Next, as shown in FIG. 2(C), the lead (16b) of the semiconductor device α mountain is cut using a lead cutter (FIG. 1(7j)) and separated from the frame portion 071 of the lead frame (2). Next, as shown in FIG. 2(d), the electric contact α mallet of the tester (FIG. 1(8)) inserts the semiconductor device between the lead (18b) and the lead frame (2). The frame portion aη is contacted, and the electrical characteristics of the semiconductor devices 0 to 0 are measured. Based on the measurement results, as shown in FIG. 2 (8), the print (I9) is )).
次に、第２図（ｆ）に示すように、リードカッタ（第１
開明）′を用いて、半導体装置Ｑωの残りのリード（１
６ａ）が切断され、砕０ηよ、り半導体装置（Ｉ５）が
分離され、半導体装置ａ■が完成する。Next, as shown in FIG. 2(f), use a lead cutter (the first
The remaining leads (1) of the semiconductor device Qω are
6a) is cut, and the semiconductor device (I5) is separated by 0η to complete the semiconductor device a2.
以上の説明の通り、本発明によれば、半導体装置の組立
及び最終検査などが、極めて合理的に、短時間でなされ
、途中のストックや途中の取扱いがないため、原価も安
くできるようになる。As explained above, according to the present invention, the assembly and final inspection of semiconductor devices can be done extremely rationally and in a short time, and the cost can be reduced because there is no intermediate stocking or handling. .
以上の説明では、最終検査の後に印刷を行なったが、検
査結果により印刷の内容が変らないものであれば、印刷
も先に行なっても良い。In the above explanation, printing was performed after the final inspection, but printing may be performed first as long as the content of the print does not change depending on the inspection results.
又、本発明は、トラ／ジヌク、ダイオード、サイリスタ
、集積回路など、全ての半導体装置の製造に適用できる
のはもちろんである。Moreover, the present invention can of course be applied to the manufacture of all semiconductor devices such as diodes, thyristors, integrated circuits, etc.
１ｊｌ１図は本発明方法の概要を示す構成図、＃Ｉ２図
は本発明方法の各工程の詳細を示す斜視図である。
図において、（１）は供給リール、（２）はリードフレ
ーム、（３１はフレーム送り機、（４）はダイボ／ダ、
（５）はワイヤボンダ、（６）は封止機、（７）及び（
イ）はリードカッタ、（８）はテスタ、（釦は印刷機、
（１１）は巻取りリール、（Ｉ２）は半導体ペレット、
Ｃ１１は金細線、ａ彎は樹脂、輛は半導体装置、（１６
ａ ）及び（１６ｂ）はリード。
αηは枠部、ａｌｌは接触子である。
なお、図中同一符号は同一または相当部分を示す。
代理人 葛野信−
第２図
！６に
第２図Figure 1jl1 is a block diagram showing an outline of the method of the present invention, and Figure #I2 is a perspective view showing details of each step of the method of the present invention. In the figure, (1) is a supply reel, (2) is a lead frame, (31 is a frame feeder, (4) is a die/da,
(5) is a wire bonder, (6) is a sealing machine, (7) and (
A) is a lead cutter, (8) is a tester, (button is a printing machine,
(11) is a take-up reel, (I2) is a semiconductor pellet,
C11 is a thin gold wire, the a-curve is a resin, the body is a semiconductor device, (16
a) and (16b) are leads. αη is a frame portion, and all is a contact. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Makoto Kuzuno - Figure 2! Figure 2 in 6
Claims (1)
されるり−ドと、上記枠部に一端が保持されて上記半導
体ベレットの電極と結線されるリードとからなる半導体
装置−成区分を連続して設けた長尺状のリードフレーム
を連続的に送りながら、上記半４体ベレットの固着、上
記半導体ベレットの電極とリード間の結線および封止を
順次行なって上記長尺状のリードフレーム上に半導体装
置を順次形成し、しかる後に、上記リードを少なくとも
１つを除いて上記枠部より切断して上記半導体装置の特
性検査を行なった後、上記残り、のリードを上記枠部よ
り切断して上記構成区分毎の半、ｌＩ犀表直を上記リー
ドフレームから分離することを特徴とする半導体装置の
製造方法。A semiconductor device consisting of a wire having one end held by a continuous frame portion to which a semiconductor pellet is fixed, and a lead having one end held by the frame portion and connected to an electrode of the semiconductor pellet. While continuously feeding the elongated lead frame provided on the elongated lead frame, fixing of the semi-four pellets, connection and sealing between the electrodes and leads of the semiconductor pellet are performed in sequence, and the elongated lead frame is placed on the elongated lead frame. Semiconductor devices are sequentially formed, and after that, the characteristics of the semiconductor device are inspected by cutting all but one of the leads from the frame, and then cutting the remaining leads from the frame. A method for manufacturing a semiconductor device, characterized in that the half and half sides of each of the constituent sections are separated from the lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9939281A JPS58134A (en) | 1981-06-24 | 1981-06-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9939281A JPS58134A (en) | 1981-06-24 | 1981-06-24 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58134A true JPS58134A (en) | 1983-01-05 |
Family
ID=14246218
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9939281A Pending JPS58134A (en) | 1981-06-24 | 1981-06-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58134A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59204245A (en) * | 1983-05-06 | 1984-11-19 | Mitsubishi Electric Corp | Resin sealing process of semicondutor device |
| JPS63184344A (en) * | 1987-01-26 | 1988-07-29 | Toshiba Corp | Equipment for manufacturing semiconductor |
| JPH01266726A (en) * | 1988-04-18 | 1989-10-24 | Sanyo Electric Co Ltd | Assembling apparatus for semiconductor device and measuring method therefor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5326670A (en) * | 1976-08-25 | 1978-03-11 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS5499564A (en) * | 1978-01-12 | 1979-08-06 | Citizen Watch Co Ltd | Manufacture of semiconductor device |
-
1981
- 1981-06-24 JP JP9939281A patent/JPS58134A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5326670A (en) * | 1976-08-25 | 1978-03-11 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS5499564A (en) * | 1978-01-12 | 1979-08-06 | Citizen Watch Co Ltd | Manufacture of semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59204245A (en) * | 1983-05-06 | 1984-11-19 | Mitsubishi Electric Corp | Resin sealing process of semicondutor device |
| JPS6361775B2 (en) * | 1983-05-06 | 1988-11-30 | ||
| JPS63184344A (en) * | 1987-01-26 | 1988-07-29 | Toshiba Corp | Equipment for manufacturing semiconductor |
| JPH01266726A (en) * | 1988-04-18 | 1989-10-24 | Sanyo Electric Co Ltd | Assembling apparatus for semiconductor device and measuring method therefor |
| JPH0646641B2 (en) * | 1988-04-18 | 1994-06-15 | 三洋電機株式会社 | Semiconductor device assembling apparatus and its measuring method |
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