JPS58133006A - Power supply circuit of amplifier - Google Patents

Abstract

PURPOSE:To reduce the power loss of a power amplifying circuit and to increase the power efficiency for a power supply circuit of an amplifier, by actuating the power supply circuit with the voltage of a level when the signal level is low. CONSTITUTION:Now it is supposed that the signal level is low and set at¦vO- VC¦<¦VCC2¦. As a result, a power supply transistors (TR)Q3 and Q4 are turned off with diodes D1 and D2 turned on respectively. Therefore the feed is carried out to the collectors of amplifying TRsQ1 and Q2 with a low level of voltage + or -VCC2. Thus a current of¦VO+VC¦is supplied instead of¦VCC2¦. In such a way, a power supply circuit is actuated with the voltage of a low level when the signal level is low. Thus, the power loss is reduced and the power efficiency is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power supply circuit for an amplifier, and more particularly to a power supply circuit for a power amplifier.

In conventional power amplifier circuits, the power supply voltage is set constant and supplies power to the output amplification transistor, so the power supply voltage level is a high value determined by the maximum power required by the load. It has become. Therefore, even when the signal level is small, this high power supply is being fed to the output amplifying transistor, so the power loss due to this transistor is relatively large, resulting in poor power conversion efficiency and a large radiator for heat dissipation. This prevents the miniaturization of Soso. In audio equipment, the average input signal level is generally small, so the above problem is significant in audio power amplifiers.

An object of the present invention is to provide a power supply circuit with a simple configuration that can reduce power loss in a power amplifier circuit and improve power efficiency.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention, in which an input signal e is supplied via a bias circuit 1 to a power amplification stage 2 comprising a pair of complementary output transistors Q, . Both transistors Q, , Q, have an emitter follower configuration, and each emitter follower output is connected to a resistor R1, R,
Push-pull drive the load Rt.

A low level power supply ±VCC is supplied to the collectors, which are power supply terminals (A, B), of both transistors Q, , Q, respectively, via diodes D, , i). Also, capacitors C1 and C2 are provided, both capacitors C
0 and C6 are charged to a constant voltage ±Vc by the divided voltage output of a voltage dividing circuit including resistors R5, R, and R, R6. One end of each of these capacitors C1, C, is commonly connected to the circuit output (vo), so that the voltage at the other end of the capacitor +C, , C, is the so-called l v0 + Vel, where the output v0 and the charging voltage are superimposed. This becomes a bootstrap voltage. These bootstrap voltages are 1 V
o+Vcl is resistance R'? , i% serves as the base input of transistors Q, , Q, and these transistors Q, , Q, are amplification transistors Q,
, Q.

are connected in cascade. Then, by configuring both transistors Q, , Q, to operate as emitter followers, the pace of the transistor Q, , , Q, is approximately the same, so that the transistor Q, ,
It operates so that it is supplied to the collector of Q.

Note that the diodes D, , D4 are transistors Q, , Q
, for base-emitter reverse voltage protection. Further, the voltage Vcc is the collector power supply of the transistors Q, , and Q.

In such a configuration, the signal level is low. +vc
If l (l Vccs I, then transistors Q, , Q, are off and diodes D, ,
D is on, so that the collector of the amplification transistor QlsQ is supplied with power from a low voltage VC.

On the other hand, the signal level increases and l p0+V, l≧IV
cczl, transistors Q, , Q, turn on and diodes D, , D, turn off. Therefore, the power supply to the collectors of transistors Q, , Q, is
Transistor Qs IQ, I Vcc
A current of Iuo-1-vcl will be supplied instead of sI.

FIG. 2 is a waveform diagram showing the above-described operation of the circuit of FIG. 1, and the waveforms A and B are the respective collector voltages of the transistors Q1 and C2. The voltage indicated by Vc is bootstrapped by a capacitor and is an offset voltage. This voltage ■. are the resistors R3, R, and R of the voltage divider circuit
's, is determined by the resistance ratio of R11 and the power supply V, c.

As described above, according to the present invention, since the circuit operates with a low voltage when the signal is small, the power loss is significantly improved compared to the conventional circuit, so the heat sink can be made smaller, and the device can be made smaller. It is something.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is an operating waveform diagram of the circuit of FIG. Explanation of symbols of main parts C, , C, ... Capacitor D, , D
2 ・・・・・・Diode Q,,Q, ・
......Amplification transistor Q,,Q,...
...Power transistor applicant Motohiko Fujimura, agent of Pioneer Corporation, patent attorney Figure 2 ◆ vctI 1---11111-%cj

Claims (1)

[Claims] A power supply supplying power to an amplifier, a charged capacitor whose terminal voltage reaches a predetermined value, and a superimposed voltage obtained by superimposing the output voltage of the amplifier and the charging voltage of the capacitor, which is larger than the voltage of the power supply. A power supply circuit for an amplifier, comprising means for supplying the superimposed voltage to the amplifier instead of the voltage of the power supply when the power supply voltage is exceeded.