JPS58132964A - Preparation of semiconductor device - Google Patents

Abstract

PURPOSE:To form shallow emitter base junction with good controllability at a low temperature by snow raking effect during heat processing. CONSTITUTION:An oxide film part 5 on a base region 7 is removed by etching, a platinum layer 11 is vacuum deposited after opening a contact hole 10 and thereafter heat processing is carried out. At this time, the Pt layer 11 connected to the base region 7 becomes PtSi layer and a base contact region 12 is formed, and arsenic doped polycrystalline silicon patterns 91, 92 are converted respectively to the PtSi layers 131, 132. The arsenic in the arsenic doped polycrystalline silicon patterns 91, 92 is swepted out in high concentration by the snow raking effect to a part of the surface of base region 7 and epitaxial layer 3 and thereby the n<+> type emitter region 14 and n<+> type collector leadout region 15 are formed. Thereby, the preformed p type base region 7 is prevented from spreading in the depth and lateral directions.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to an improvement in a method for manufacturing a semiconductor device.

[Technical background of the invention]

Conventionally, a semiconductor device, for example, a pie I-La transistor, has an n-type epitaxial layer on a semiconductor substrate of a first conductivity type, for example, a p-type, a p-type base region on a part of the surface of this epitaxial layer, and a space region. Part of the surface! 1+
They were manufactured through steps such as sequentially forming mold emitters and ridge areas.

[Problems with background technology]

However, in the above-mentioned manufacturing method, in the high-temperature heat treatment when forming the emitter region, the base region that has already been formed expands in the depth and lateral direction, making it difficult to form a shallow bond, and This has the disadvantage that it is difficult to control the pace width.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a method for manufacturing a highly integrated, high-speed semiconductor device that can realize shallow junctions.

[Summary of the invention]

In the present invention, when a silicon pattern doped with a second conductivity type impurity formed in an opening of an insulating layer on a semiconductor substrate or a semiconductor layer is silicided at a low temperature, impurities in the four turns of the silicon are removed by snow removal. The main idea is to introduce it into the substrate or semiconductor layer to form a semiconductor region of the second conductivity type without causing any adverse thermal effects as in the prior art. To explain the snow shoveling effect in detail, even if the silicon glossy turns are only superficially silicided, the silicided metal layer abnormally diffuses along the grain boundaries existing in the silicon 4 turns. - The vicinity of the interface between the middle turn and the substrate or semiconductor layer is silicided, creating a snow shoveling effect. Regarding this snow shoveling effect, bulk S1 containing impurities on the surface
A method of re-diffusion by siliciding the surface area of the substrate has already been proposed by Appl.

Phys, Lett,, Vol, 38, A 12
(1981) P, 1015, the present inventor discovered for the first time the phenomenon of silicidation of a silicon pattern and the flushing of impurities in the silicon pattern to the substrate or semiconductor layer.

[Embodiments of the invention]

An example in which the present invention is applied to a bipolar transistor will be described with reference to FIGS. 1(a) to 1(f).

[1] First, an As dope oxide film (not shown) was formed on a p'' type silicon substrate 1 with a resistivity of 18 to 25 Ω and α, and then an oxide film/mother turn was formed by photolithography. .

Subsequently, heat treatment is performed to diffuse arsenic from this oxide film onto the surface of the substrate to selectively form an n+ type buried layer 2 having a specific resistance of 20 to 30 ΩA. Subsequently, after removing the oxide film/gutter, a film with a thickness of 1.0 μm and a specific resistance of 0.2 Ω is deposited on the substrate 1 using a normal vapor phase growth method.
An n-type epitaxial layer 3 serving as a collector region was provided. Next, p+ type isolation regions 4, 4 reaching the substrate 1 were selectively formed in the epitaxial layer 3 (see Fig. wc1 (
,) as shown).

[11] Next, apply a layer of 0.2 on the above-mentioned pitaxial layer 3.
After growing a thermal oxide film 5 with a thickness of -μm and applying a resist film (not shown), holes were formed in the resist film t in the planned space area by photolithography. A turn-shi was formed (Fig. 1 (
b) As shown). Next, zolon was applied to a predetermined position of the epitaxial layer 3 as a mask of the resist film 76f at an acceleration voltage of 85@V and a dose of 1×10 pieces.
After ion implantation under the following conditions, the arm turn 6 of the resist film was removed. Thereafter, heat treatment was performed at 1000°C for 1 hour in a nitrogen atmosphere to give a thickness of 0.4 μm and a resistivity of 600 Q10.
A mold base region yl was formed. Thereafter, the oxide film 5 was selectively etched to form openings 8seljs' in the portions where the collector was to be taken out.

Subsequently, after depositing an arsenic doped polycrystalline silicon layer (not shown) to a thickness of 500 mm over the entire surface, the polycrystalline silicon layer is patterned to form openings 81, 8 . The arsenic polycrystalline silicon layer 4 covers the oxide film 5 and partially extends beyond the oxide film 5.
Turn 9 Sumire.

9st was formed (as shown in Fig. 1(,)).

[011] Next, after removing a part of the oxide film 5 on the base region 7 by etching and forming a contact hole 10, a beam evaporator is used to deposit platinum (p2) to a thickness of 5 oool over the entire surface.
t) Layer 11 was deposited (as shown in FIG. 1(d)). Subsequently, heat treatment was performed at 600° C. for 15 minutes in a nitrogen atmosphere. At this time, the PT layer 11 connected to the base region 7 through the contact hole 10 became a PtSi layer, and a base contact region 12 was formed. At the same time, the arsenic y--? Polycrystalline silicon Noreen'1+92 is ptss
Layer 131.13. were converted into . In addition, during this heat treatment (silicidation), arsenic in the arsenic dog polycrystalline silicon mother turf 91e9m is swept out at a high concentration onto a part of the surface of the pace region 7 and the epitaxial layer 3 due to the above-mentioned snow shoveling effect, Thickness 0.2μm 1 Specific resistance 20Q/E
), an n+ type emitter region 14 and an n+ type collector extraction region 15 were formed. Next, the remaining PT layer 11 was removed by aqua regia treatment (as shown in FIG. 1 (@)).

The thus formed base region 7, edge region 14t
- The impurity profiles of zolon and arsenic formed respectively are shown in the characteristic diagram shown in FIG.

Here, (4) in the figure shows the impurity profile of zolon, and (B) shows the impurity profile of arsenic. Note that (c) is the epitaxial layer 3
The impurity profile of phosphorus forming is shown.

Ov) Next, an AA-Fli layer with a thickness of 1.0 μm was deposited on the entire surface and patterned to form a turn 1 of the At-8i layer.
Base electrode 77 consisting of At-8i layer turn 163, Emitter electrode consisting of At-8i layer turn 163
Collector extraction electrode 19 consisting of layered turn 161
A desired bipolar transistor tm was constructed by forming each of the following (as shown in FIG. 1(f)).

However, according to the above-described manufacturing method, low temperature (fi 0
When forming the Pt81 layer 131elSz by siliciding the arsenic doped polycrystalline silicon layer under 0°C), the n-type emitter region 14 can also be formed at the same time.
It is possible to suppress the mold base region 7 from expanding in the depth and lateral direction,
Since the process design can be simplified and one shallow junction can be formed, high integration and high speed devices can be achieved.

In addition, as mentioned above, arsenic doped polycrystalline silicon can be produced at low temperatures.
In order to perform 4 turns of silicide, the emitter area 14
The introduction of contamination and the occurrence of defects during formation can be suppressed, and transistor characteristics can be significantly improved.

Furthermore, since the PTS layer 131 is present on the semiconductor region 14 in the process, the At-Si layer thickness turn 163 does not touch the emitter base junction, improving the reliability of the device. The resistance between the layer pattern 11j and the emitter region 14 can be kept low.

Incidentally, in the above embodiment, the emitter region, the collector extraction region were formed at the same time as the arsenic dope polycrystalline silicon/rubber turn was silicided, but the present invention is not limited to this. -! Even if the arm turf, which has a two-layer structure consisting of a polycrystalline silicon pattern, is silicided, the same effect as in the above embodiment can be obtained. The same effect can be obtained even if arsenic is ion-implanted into an undoped polycrystalline silicon arm turn, and then the arm turn is silicided.

The present invention is not limited to the case of bipolar transistors as in the above embodiment; MO8) Can be similarly applied to transistors. However, the semiconductor region of the second conductivity type formed by the above-mentioned snow shoveling effect is the collector region in the case of an IL, and is the source/drain region in the case of a MOS transistor.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to form shallow emitter-base junctions at low temperatures with good controllability, and it is possible to provide a method for manufacturing highly integrated and high-speed semiconductor devices such as transistors.

[Brief explanation of drawings]

1(a) to 1(f) are cross-sectional views showing the manufacturing method of a bipolar transistor according to an embodiment of the present invention in the order of manufacturing steps, and FIG. 2 is a base region of the bipolar transistor shown in FIG. 1(f). FIG. 3 is a characteristic diagram showing the profiles of impurities forming the , emitter, and epitaxial regions and the epitaxial layer tube. DESCRIPTION OF SYMBOLS 1...p- type silicon substrate, 2...n+ type buried region 3...n type epitaxial layer, 4...p++ isolation region, 5...oxide film, 7...p type base area, 81
,8゜...opening part, 91e9m...arsenic dog polycrystalline silicon glossy turn, 10...contact hole,
11...Platinum layer, 12...Base contact 1ijL
1sz13 years...ptst layer, 14...n+
+ emitter area, 15...- type collector extraction area,
161'? I6s...5i-At layer number turns,
17...Pace 'It pole, 1'...Work <Ivy electrode, 19...Collector extraction electrode. Applicant's representative Patent attorney Takehiko Suzue Figure 1 (a) (b) (C) Figure 1 (e) 1'11

Claims (1)

[Claims] a step of providing an opening in an insulating layer on a semiconductor substrate or semiconductor layer of a first conductivity type; and adding an impurity of a second conductivity type to the opening so that a portion thereof extends to the surrounding insulating layer; forming a silicon ivy turn, and forming a second conductive semiconductor region by siliciding the silicon ivy turn and selectively introducing impurities of a second conductivity type into the substrate or the semiconductor layer. 1- A method for manufacturing a semiconductor device, comprising: