JPS58130619A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To increase the carrier frequency of a PWM wave, by having a double system for a latch circuit, a comparator and a sweep counter respectively and to increase the output pulse frequency of a pulse generating system at the upper bit side. CONSTITUTION:Latch circuits 31 and 32 latch lower 5 bits and upper 6 bits. A comparator 37 applies a coincidence signal of contents between the circuit 32 and an up-counter 38 to FF41 and 42. When the output of the counter 38 is ''0'' or ''63'', the FF41 and 42 are set respectively. It is same with a comparator 33. The outputs of FF circuits 41, 42 and 43 are connected to each gate respectively. If the wave detection quantity is set as 750=B''01011101110'', the upper 6 bits and lower 5 bits are set at 23 and 14 respectively. Therefore the high level period of the output A is equal to an amount equivalent to 14 counts. A pulse is delivered 18 times from a gate circuit in a high level period of an output C, and the high level periods of all cycles become 750 in total. Thus a PWM wave corresponding to the wave detection quantity is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital-to-analog converter C2, which is suitable for use, for example, in a digital servo device of a video tape recorder.[Technical Background of the Invention] ] In recent years, a digital servo system based on digital signal processing has been adopted as the servo*iii for the capstan motor and rotary rad motor g2 of video tape recorders (hereinafter referred to as VTR). , (a) High precision.

(- There is no change during maintenance, (c) Parts variation (= avoidance of influence), so semiconductor integration is also being carried out. 1 evil 1:
The configuration is as shown below.
2 is the reference signal RIF (e.g. vertical synchronization signal) branch output) (from Yu, the number (initial data) of the memo 9ti is preset, and the O-day 1 circuit 2J, which carries the count data of the clock CP, is used for measurement. This is to stop the clock CP1t'll to obtain normal operation when the counter 12 is preset.
When the JM is input (for example, the comparison signal is a rotation detection pulse of a rotary head), the data of the O latch circuit 13, which is a circuit that latches the contents of the measuring counter 12, and the count data of the counter 16 are compared by a comparator tSt: It is.

The coincidence pulse is applied to the set terminal 6 of the flip-flop circuit 11 and the reset terminal of this flip-flop circuit 17 (; is added to the carry C1<Y of the counter 16.0 Therefore, from the solid-flop circuit 17,
Contents C of the wrap circuit 17 whose cycle is the number of stitches of the clock UP of the counter 16; A pulse width modulated output with a corresponding pulse width is obtained.

This latch circuit 14 holds the data of the upper (t-in) bit of the measurement counter 12.

A certain linear control range is installed.

When this range Y is exceeded, the duty of the pulse width modulation output is fixed T by controlling the linear range limiting circuit l#. The pulse width modulation output is converted into a DC control voltage (-) by the low-pass filter 19, and is applied to the motor drive Circuit C: Input ・The above is the function of a so-called digital detector. Then, the pulse width modulation output Y of the duty corresponding to the phase difference 6 is obtained, so if you want to make the phase difference constant, the DC control voltage C; ) to control the rotational frequency Y of the motor.This amazing digital servo device is a patent application No. 139337/1986, patent application No. 139337, 1983, which was published by human power.
-155122, Japanese Patent Application No. 56-155153, Taiho No. 56-139338, Japanese Patent Application No. 56-165124, etc.i; A D/A conversion is performed to change the width of the curse and convert it to VDC. (;There is the following problem. In other words, Low!<Sfilter 19
This filter removes the carrier component (the carrier frequency of the PWM wave), but this filter exists in the servo loop.

This is a factor that causes a one-phase delay in the loop response. Therefore, if we consider the detection accuracy (resolution) for phase error detection, it is better to reduce the phase delay by 1 (- means the higher the carrier frequency of the 1M wave is, the more servo). You can obtain finer resolution by increasing the number of bits (e) as much as possible.

Incurring an increase in the number of bits of the D/A g conversion counter (secondary) If we try to increase the carrier frequency IMw of the PIA/M wave, of course the frequency of the Glock CP must be taken very seriously. O For example, change the carrier frequency of the PWM wave to the servo loop number - 2 so as not to affect it.
0 kHz C installed.

On the other hand, if the number of bits in the counter that increases fl# degrees yyFi is 11c = 2048), then the clock frequency is
20 K)it X 2048ki4 Q M)1z C
Inevitably, it would be extremely difficult to handle it with an integrated circuit. [Object of the Invention] This invention was made in view of the above circumstances, and the PV
It is an object of the present invention to provide a digital-to-analog converter that can easily raise the carrier frequency of W waves to a sufficiently high level and that can also achieve high bit accuracy. [Summary of the Invention] Bit, lower bit latch circuit 3
1.32 to share the contents of the measurement counter 12,
The content of each latch is set to l, and the second comparator 3
J1.81g: Enter ◎41. a second comparator,
The sweep take for 9J and J7 is the ripple counter s.
4. 0 obtained from the synchronous counter 38. In this case, the ripple counter 34 is used as a carry V clock for the synchronous counter 38.

2 systems of supplementary counters (2, the W pulse frequency of the upper bit side pulse generation system is increased) [Embodiments of the Invention] Hereinafter, embodiments of the present invention will be explained with reference to the drawings. !
In Fig. 12, 12 is a measurement counter, and when the reference signal REF is input, the constant of the memory 3 is preset and the count of the Glock CP- is started. For example, the contents of the lower 5 bits and the upper 6 bits are
This is a circuit that latches when the comparison signal etm is input. ◎ The contents of the latch circuit 32 that latches the upper 6 bits are comparator S7 ≦ 2. This comparator 37
The count output of a 6-pit synchronous up counter S8 is also added to I;. The comparator 32 is the latch circuit 3
When the 8th valley of 2 and the gatekeeper of up counter S8 match, a match pulse is output, and this pulse is sent to flip-flop circuit 4.
1.42 each reset terminal 1: Add/Furthermore, the output contents of the above up counter 1# are @0” detection circuit S9,
63" detection circuit 40I is also added, and when the output content of the up counter 38 is "0#", the flip-flop circuit 41 is set, and when the output content of the up counter 38 is "°63", the flip-flop circuit 41 is set. The output of the latch circuit 81 of the lower 5 bits is input to one of the comparators sl, which is configured to set the latch circuit 42.
The output of the 5-bit rip-up counter j4 is added to the other input terminal C2 of the 5-bit ripple counter 14.The M8B output of the 6-bit synchronous up counter 38 is used as its clock.Comparator 33 outputs a C match pulse when the output of the ratte circuit 31 and the output content of the ripple up counter 14 match, and this output is applied to the reset terminal of the ripple up counter 84 of the ripple up counter 84.
The output of ``O'' detection circuit 15g- is also added, and 1
When 0# detection is obtained, the flip-flop circuit 3
The output of the flip-flop circuit 41 and 42, to which the detection pulse is applied to the set terminal of 6, is the output of the AND circuit 4.
The output of the flip-flop circuit 36 is applied to the input terminal of the flip-flop circuit 3#44.

The second input terminal C of the AND circuit 42 is applied directly, and the 111112 input terminal C of the AND circuit 43 is applied via the inverter 46f. ◎And the AND circuit 4j.

The output of 44 is input to the OR circuit 45.0 Figure 3 is a time chart of this circuit, and m31Jf is the output of counter 3.
The 6-bit contents of B.

This shows a situation in which the contents of the 5 bits of the counter 34 change sequentially. Further I: 3rd af*sf1 is °0#
Small detection 39 and "631 indicate the output Y of the detection circuit 40. Also @ 3 "a f + is the output of the °o' detection U path 35 0 If the upper counter jJc@0' is latched now (I will explain this in detail.) When @0' is latched in the counter 12, the comparator 32 outputs *aVf
s is obtained. Therefore, in this case, the flip-flop circuit 42 matches the output from the "63" detection circuit 40 and the pulse I: Therefore, it is reset, so the outputs A and B of the flip-flop circuit 41641 are % As shown in FIG.
Furthermore, if the latch circuit at is also latched at °O"t, the coincidence pulse of the comparator 3J is
- As shown (2) At this time, the output of the Om detection circuit q5 is also added to the flip-flop circuit 36, so the output (O is C as shown in Fig. 3);
Does not change, therefore, the upper and lower latch circuits 32.
When the (c) valley of 31 is @00'', the PWM output of the OR circuit 45 is at a low level as shown in Figure 3, '1m4' knee.

Next≦2 When the content of the upper bit latch circuit 32 is @01° and the content of the lower bit latch circuit 31 is @1m, the comparator 31 selects the 32nd! ! The output shown in J f■'2 is obtained. Therefore, the flip-flop is rotated and the third
Figure f1. The coincidence pulse (- is therefore reset, so
Obtaining the pulse shown in IJ3 diagram f1m C second and third
The AND circuit 44C takes the logical product of the pulse in Figure f11 and the pulse shown in Figure 3, and the 1'WM output becomes the pulse shown in the third factor. When the content of the circuit 32 is "0" and the content of the lower bit wrap circuit 31 is 2', the output power shown in the 31st erts is obtained from the comparator 33. Therefore, the flip-flop circuit wIs th )t,
o"ms times g s s is set as 2!, and the coincidence pulse of Fig. 3 f□ (: Therefore, it is reset, so the third
In this case, the PWM output becomes the pulse shown in Figure 3. If the content of the bit ratte circuit 31 is "31", the rtt a fl@@fl16 shown in Figure 3
:Show time chart Hata 3 elJ ft
v is the coincidence pulse obtained from comparator 33, I! 3
Figure fts is the output of the flip-flop circuit 36, Figure 3f
ll is the PWM output ◎ Fig. 3 f1゜ shows that the same capacity of the upper layer and the tlatte circuit 32 is 1.
1'', the comparator 37 or P)4 shows one pulse.The 31st Wf□, f2. is the flip-flop circuit 41. when ng of the latch circuit 32 is ``11'' as described above. 42 output pulses are shown.

In Fig. 3 f□, the contents of the upper bit wrap circuit 32 are °1.
-, the contents of the lower bit latch circuit 3 are changed to °O“
Figure 3 shows the PWM output when o 1%
No. 1 is the PW when the content of the upper and lower level circuits 32 is '1m, and the content of the lower and lower level circuits 31 is also l'.
Fig. 3 f, which shows the M output, is the coincidence pulse obtained from the comparator 37 when the equivalent capacity of the upper bit ratte circuit 32 is "63";
□ is the output of flip-flop circuits 4J and 4j at this time.

The third m fma indicates the P%VM output when the content of the upper bit latch circuit 32 is "63" and the content of the lower bit latch circuit 31 is "0".
3 shows the PWM output when the content of the upper bit latch circuit 32 is 1630 and the content of the lower bit latch circuit 3 is "°]".F and o in FIG. 3 show the PWM output of the upper bit latch circuit 32. Is the PWM output incorrect when the content is 63# and the content of the lower bit latch circuit 31 is "31"? This circuit operates as described above. For example, the digital detection wax is 750 = B"01011101110', the upper 6 bits are B@010111''=
23. The lower 5 bits are b'''01110'' = 14. Therefore, the high level period of the output (A) of the flip-flop circuit 41 is the 0 gate circuit (AND circuit 4B, 44. etc.) from.

The high level period of the output υ of the flip-flop circuit 36 (
:, output (B) is 14 [! ! 1. Output prisoner is 32-14=
The pulse is output 18 times, and the total high level interval in the entire cycle is 14X24+18X23=336+414.
= 750, and a PWM wave corresponding to the digital test material C2 can be obtained. 0 flip-flop circuit 36.41
．． The terminal marked 0 shown in 42 is a terminal terminal.

The 0-wire circuit is designed to prevent malfunctions caused by competition between the set pulse and reset pulse, and to obtain linearity in digital-to-analog conversion. is a 6-bit synchronous up counter, and the speed of the ripple up counter with respect to the lower 5 pits (2) does not matter, and the system speed of the loop using the D/A converter can be the same as above. Effect] As mentioned above, this invention (according to the second invention, even if the response speed of the element is not changed, the business can be relatively improved)
'WM limb Y can be generated and the number of filter times can be reduced, so the response can be improved as well.Also, there is no need to reduce the number of bits, and the bit accuracy is also good Name: Can maintain C

[Brief explanation of drawings]

The first factor is a configuration explanation factor of a conventional digital-to-analog converter, FIG. 2 is a configuration explanatory diagram showing an embodiment of the present invention, and the third factor is
Figures f1-f,. The following describes the circuit operation of the second cause (1) The time chart shown in Fig. 12--Measuring counter, 9 J, 32...
Latch circuit, J3, . 1 F... comparator,
34...Ripple up counter, J5.39...
“Om detection circuit S36.41.42...Flip-flop circuit. 38...Synchronized up counter, 43.44...AND circuit〇Applicant's attorney Takeshi Suzue

Claims (1)

[Claims] When the first pulse is input, the first clock t counts m pips) (m is a positive whole number), and the lower order of this measuring counter t pips) (t is a positive number). Integer) and the contents of the upper (m-1) bits When the pulse of Y@2 is input, the lower bit latch circuit and the upper bit latch circuit respectively latch the lower bit latch circuit and the upper bit latch circuit, and the clock of i@2 is manually input to the upper bit. A synchronous counter with the same bits as the latch circuit, a ripple counter with the same bits as the lower bit latch circuit in which the clock signal of this synchronous counter is input as a clock, the contents of this ripple counter, and the lower bit latch L!l!l A comparator that is applied to the reset terminal of the flip-flop circuit of the match pulse Y%1 obtained when a match is detected by comparing the content of Then, a lth °Om detection circuit that applies the detection pulse 1 to the set terminal of the first flip-flop circuit compares the contents of the synchronization counter with the upper bit latch circuit to detect a matching state. A second comparator adds the reset terminal (Y) of the second and third flip-flop circuits to the first pulse 1 obtained when the second comparator and the minimum value of the contents of the synchronization counter 'Ik: detect the detected pulse means for detecting the maximum value of the contents of the synchronous counter and applying the detected pulse to the set terminal C of the flip-flop circuit 'g & The outputs of the three flip-flop circuits are applied to one input terminal C, respectively, and the other input terminals (- are the first to which the inverted and non-inverted outputs of the first Fujitsubu flop circuit are applied, respectively).
A digital-to-analog switching device 6 characterized in that it is equipped with an M2 AND circuit and a low-pass filter to which the outputs of the first and second AND circuits are added.