JPS58129660A - Imformation processor - Google Patents

Abstract

PURPOSE:To improve the efficiency of bits in a cache memory by making a branch address memory generate a forecast instruction address to use the address for prefetching. CONSTITUTION:A comparator 103 compares the address of an instruction in execution with a forecast instruction address, and when both addresses coincide with each other, retrieves whether a branch instruction address coincident with the latest forecast instruction address exists in a branch address memory 107 or not when there is an idle area in a forecast instruction address stack 101. When there is the brahch instruction address, an address to be branched which is stored correspondingly to the address is used as the forecast instruction address to be executed in the succeeding step. In case of absence, the increased value for the latest forecast instruction address is stored in the forecast instruction address stack 101 as the succeeding forecast instruction address. A forecast instruction address obtained by increasing together with said increased value is prefetched in the stack 101.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides information 46 for executing a program including branch instructions.
11 device.

Conventionally, the information processing device has been equipped with a catfishing method to improve the hit rate of catfishing by 5%. How to increase the size of Kti, how to increase the size of Catch Memo Vt, how to format the data in Catchie memory so that the size of the vine is optimized, and which plotter 0 order is used. Following this, there is a function #I& in which the existing sweep command is retrieved in advance, that is, it is prefetched. The 30th briftch method is effective for pigeonholes where the paired addresses to be deepened are layered in increments of 1 JI-fi, but is ineffective when the addresses to be executed are discontinuous; 10 Since the capacity is limited, other valid data may be pushed out of the cache.

Therefore, performing such a brief fetch even to a distant address will have an adverse effect. However, in general, when performing a glyph fetch, unless you advance to an address beyond a certain point before executing it, even if a valid address has been glyph fetched, the load to the cache memory will not be completed at the stage of executing that address. Not completed. This has the disadvantage that there is a waiting period for processing, which weakens the effect of briefetching. As described above, brief fetching has both advantages and disadvantages, so it has been extremely difficult to effectively utilize brief fetching.

An object of the present invention is to use a branch address memory for storing a branch instruction address and a branch destination address in pairs to predict the address of the next instruction in the depth instruction, and to perform a brief fetch from the predicted instruction address. An object of the present invention is to provide an information processing device configured to improve the hit rate of a carriage tool memory by performing the following steps.

The information section S device constructed according to the present invention includes a branch address programmer, a pre-instruction address stutter, a 'kP' and a comparator. The branch address message stores the address of the branch instruction and the branch destination address of the branch instruction as a pair. The predicted instruction address stack holds the predicted instruction address, and the comparator compares the address of the instruction being executed with the child instruction address. As a result of the comparison, it was found that the two matched, and 9! If there is a no area, a search is made to see if there is a branch instruction address in the branch address memory that can match the latest pre-adjusted instruction address. If a matching branch instruction address is found, the branch destination address is set as the next pre-instruction address to be executed since it has not been stored correspondingly.

4, and if no matching branch instruction address is found, the predicted instruction address suit is incremented with respect to the latest predicted instruction address and the larger value is set as the next predicted instruction address! It is stored in ζ and incremented along with this, and a pre-fetch is performed from the nine predicted instruction addresses in preparation for the next execution.

Next, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an information processing device constructed according to the present invention. In the 11th II, the information processing device fII stores the branch address stack 1o1゜predicted instruction address stack 101. It includes a comparator 103 and the necessary parts to carry out the process described above.

Signals 201 to 2041st are signals for interfacing with other devices. A signal 201 is a signal representing the address of a branch instruction and the branch destination address of this branch instruction. When an unconditional branch instruction is executed, or when a conditional branch instruction is successfully branched, the address of the branch instruction and the branch destination address are paired and stored in the first register 10IK.
- I can chew it.

Subsequently, these addresses form a pair and are written overlappingly in the branch assistless memo 910TK. Signal 2.2 is a signal representing the address of the instruction being executed. Third Regis-1 (l
is constantly updated to indicate the address value of the instruction being executed. The pre-instruction address stack 101 holds the pre-instruction address, and the comparator 103 compares the address of the currently executing instruction from the third register 1 and the predicted instruction from the child instruction address stack 101. To compare with the address. If these addresses are
If they have the same booter address within 0, the comparator 113 determines that these addresses match. If the plotter addresses are different, compare
・It is determined that these three addresses do not match. The pre-instruction address is outputted to a pre-instruction address suiter 101 in the order of 1iK and added to a comparator 108. If the comparison 111@1 indicates a match, the branch destination address i stored in the branch instruction address J:Sub is set as the predicted instruction address for the next Kl1 line.

Comparison -1・S+ If it shows a mismatch, KFi, next pre-buchi instruction completion dore jL or predicted instruction address suit 11・1
, and comparison is performed again by comparator 10SK. If the comparators 1 and 3 detect a mismatch and then continue to detect a mismatch when comparing the next predicted instruction address and the address of the instruction in the depth, the information processing device in FIG. This is determined to be a predicted instruction, and all predicted instruction addresses stored in the predicted instruction address stack 101 are cleared. Next, a new predicted instruction address begins to be created. New predicted instruction addresses are created in the following order and stored in the predicted instruction address stack 101.

First, the address of the instruction being executed is transferred from the first register 102 to the third register 1 . Then the third
To search the contents of the branch address register 10F to see if there is a branch instruction address that matches the contents of the register 10. As mentioned above, print the branch address1.
Since the address of the branch instruction and the branch destination address are stored as a pair in 07, this search shows that the branch instruction has the same block address as the contents of the third register 1011, and the address in the plotter is the same as the first address. To check whether the value is greater than or equal to the contents of register 10.

In the above search, the 9th drum instruction and the 5th ovp are searched.
If the block address is the same as the contents of 1011, □The address of the branch instruction that satisfies this condition is stored, and the branch destination address is stored as the next predicted instruction address. Assuming this is the fourth register 11)
SK+tut. If there are more branch instruction addresses that satisfy this condition in the above search, the fourth branch instruction address closest to the address in the plotter of the contents of the first register 10 is adopted, and the branch instruction address corresponding to this branch instruction address is selected. The branch destination address stored in the fourth register 105K is saved. Next, it is set in the 40th regime-105, and the major branch destination address is reserved ◆Address suit data
0IK is transferred and the pre-instruction address stutter 10IK is retained.

In the above 0III search, the 9th branch instruction and the sth
If the plotter addresses are not the same for the o register and sets the start address of t in the 40th register 105. Next, the 9 value set in the fourth register 105 is set in the third register 106, and the contents of branch address memory 1 (l) are searched again using the contents of jin.

In this search, if the block address of the searched nine-string instruction is the same as the block address of the contents of the third register 106, the branch destination address stored corresponding to the address of this branch instruction is It is transferred to the pre-instruction address stack 101 via the fourth register 105 and held there.

However, if the block address of the branch instruction retrieved in this search is not the same as the contents of the third register 16-, the contents of the branch address message 101 will be retrieved again through the above-mentioned process. Searched.

Through the above processing, the predicted instruction address set in the fourth register 1 (1!!) is sequentially set in the predicted instruction address stutter 101.

Predicted instruction address stack 10 by step III
When the content of 1 is cleared, the comparison by comparator 103 is interrupted. However, the pre-instruction address suiter 101
Comparison is started again when one or more predicted instruction addresses are set in , and the block address of instruction ♦ during execution of ff1K of the pre-glue voltage changes.

Index memori l0IK is cache memori 110
Copy the contents of the cashier index message inside. The update information signal 204 causes the update information to be updated.
Since the contents of 10- will be updated, it will be updated as follows.
Its contents always match the contents of the cache index message inside the cache memory 11@0.

When the predicted instruction address is entered in the fourth register 10sK set 1, the index instruction 1.
■Search the contents. If this search results in 9 hits,
The block corresponding to the predicted instruction address has already been loaded into the cache memory 11@. However, if no further processing continues, KIr
Prefetch the block corresponding to i from the index memory 101 to the cache memory 110, and load the necessary contents to the index memory 109. A memory read signal 203 is sent from the index memory 10 itself to the cache memory 110.

Through the above processing, a predicted instruction address can be generated using the branch address program 10F, and the predicted instruction address can be used to increase the depth of the brief fetch.

On the other hand, when a program is executed, the branch destination address of a branch instruction has a very high probability of matching the branch destination address when the branch instruction was previously executed.

As described above, according to the present invention, a branch address memory is used to generate a pre-instruction address and this is used for briefetching, thereby improving the hit rate of the cache memory.

[Brief explanation of the drawing]

Figure 1 shows an information center according to the present invention! 1 is a 1 m boot showing an example of one device. 107...Branch address message 101--Predicted instruction address stutter 103...Comparator 102.105.1 (1,101-〇Registers 1, 4,
・・Adder 1・・・・Φindex memory 110・・Catch for me! 01-204・Fist・Signal Patent Applicant: NEC Corporation Binkinsha Agent: Attorney: Hisashi I) Ro

Claims (1)

[Claims] A large branch address memory that stores the address of a branch instruction and the branch destination address of the branch instruction as a pair, a predicted instruction address stack for holding predicted instruction addresses, and a comparator for comparing an instruction address and the predicted instruction address, and if there is an empty area in the predicted instruction address stack during a period in which the output of the comparator indicates a match, the latest instruction address is updated. The contents of the branch address memory are searched by the predicted instruction address of K, and when the address of the branch instruction matches the latest predicted instruction address, K sets the branch destination address corresponding to the address of the branch instruction to If the address of the branch instruction does not match the latest pre-distribution field instruction address, insert the latest pre-distribution side instruction address JK and write the value as the next pre-instruction address. An information processing apparatus characterized in that the information processing apparatus is configured to store the instruction address in the instruction address stutter and perform pre-etch from the previous symbol-instruction address obtained by incrementing to prepare for the next instruction.