JPS58129619A - Microcomputer device - Google Patents

Abstract

PURPOSE:To set an optimum access time in accordance with memories and peripheral devices and to attain high-speed processing by specifying the period of outputs from a clock pulse generating circuit and on/off of the clock pulse generating circuit by previously stored data. CONSTITUTION:A CPU 1 is actuated by receiving clock pulses phi0 from the clock pulse generating circuit 4. An address line ADD of the CPU 1 is connected to the input terminal of an address decode/chip select signal generating circuit 2. By receiving an address signal from the address line ADD, the circuit 2 outputs a chip select signal to specify a memory 3, peripheral devices, the clock pulse generating circuit 4, etc. The access time information of the memory 3 is written as one-bit data in a specific address 3-1 in the memory 3.

Description

[Detailed Description of the Invention] The present invention relates to a microcomputer device equipped with memories and peripheral devices each having different access times, and which can operate at the most efficient speed while reducing power consumption with a simple configuration. The purpose is to provide an excellent microcomputer device.

Generally, in microcontroller devices equipped with memories and peripheral devices that have different access times, in order to ensure accurate operation of the memory and peripheral devices, it is necessary to adjust the access time to the slower one. Therefore, in this type of device, overall This operation is not very desirable because it requires a lot of time.

The present invention eliminates the above-mentioned conventional drawbacks, and provides an excellent microcomputer device that can always set the optimal access time according to each memory and peripheral device, and can perform high-speed processing as a whole. be.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A microcomputer device according to the present invention will be described below with reference to drawings of an embodiment. FIG. 1 is a bronch diagram of one embodiment of the microcomputer device of the present invention, in which 1 is a central processing unit (hereinafter referred to as CPU), 2 is an address decoding/chip select signal generation circuit, 3 is a memory, and 4 is a block diagram of an embodiment of a microcomputer device according to the present invention.
indicates a clock pulse generation circuit.

It should be noted that, of course, a keyboard, a display 9, peripheral devices, etc. are provided, but these are omitted in FIG. 1 for the purpose of simplifying the drawing and because these are well known.

In the above embodiment, the CPU 1 receives the clock pulse φ from the clock pulse generation circuit 4. It operates according to the following. C.P.
The address line ADD of U1 is connected to the input terminal of the address decode/chip select signal generation circuit 2, and the address decode/chip select signal generation circuit receives the address signal from the address line ADD and outputs the memory 3.
9 generates a chip select signal for specifying peripheral equipment, clock pulse generation circuit 4, etc. The memory 3 inputs an address signal (lower address signal in this embodiment) from the address decode/chip select signal generation circuit 2 address line ADD, and receives the address signal from the data line DAT of the CPU 1.
Various data are exchanged through A. Then, in this memory 3, access time information of this memory 3 is written in advance at a specific address 3-1 as 1-bit data, for example, o if the speed is high, 1 if the speed is low. When the address is output, the address decode/chip select signal generation circuit 2 decodes the upper digit address of the specific address and outputs the chip select signal C8M for specifying the memory 3.

Therefore, the memory 3 receives this select signal C8M and the lower digit address of the above-mentioned specific address and selects the data line D.
The data 3-1 at the specific address is output to the ATA.

The CPU 1 then reads this data.

Clock pulse generation circuit 4 includes pulse generation circuit 4-1. Gate circuit 4-2. Synchronous delay circuit 4-3゜4-4. It is constituted by a memory circuit 4-5.

The pulse generation circuit 4-1 includes a crystal oscillation circuit 4-11 with an oscillation frequency of 41 and a frequency divider 4-1 that divides the oscillation output into %.
2, and its output (frequency f0) is applied to the gate circuit 4-2 and the synchronous delay circuits 4-3, 4-4.

The gate circuit 4-2 consists of a two-person gate circuit 4-21 whose one input is the output of the pulse generation circuit 4-1, and this OR game)
The output of 4-21 is used as one input, and a clock pulse φ is applied to the CPU1. 4-22 and this AND gate 4-2 has two ρ' outputs φ. It is constituted by an input AND gate 4-23 which has one input as one input and applies its output to the other input terminal of an OR gate 4-21. The output of the synchronous delay circuit 4-4 is applied to the other input terminal of the AND gate 4-22. AND game) 4-2
The output terminal of the address decoding/chip select signal generation circuit 2 and the memory 4-
6 is connected, and the output end is connected to a synchronous delay circuit 4-3.

The synchronous delay circuit 4-3 converts the output of the AND gate 4-23 in the gate circuit 4-2 through an inverter 4-31.
The output f0 of the pulse generation circuit 4-1 is used as a reset input.
A three-stage binary counter 4-32 whose clock input is
It consists of a three-man NAND circuit that takes the outputs A, B, and C of each stage of this counter as input and outputs them to a synchronous delay circuit 4-4, and outputs the output from the gate circuit 4-2 to a pulse generation circuit 4-1. is delayed in synchronization with the output pulse f0 from.

The synchronous delay circuit 4-4 uses the output pulse f0 from the pulse generating circuit 4-1 as a strobe input via the inverter 4-41, and outputs the output of the synchronous delay circuit 4-3 from the two-man power A.
It is constituted by a D-type flip-flop circuit 4-42 which receives a D input via an ND gate. This 797
The output of the 17091 circuit 4-42 is applied to the AND gate 4-22 in the gate circuit 4-2.

The other input terminal of the AND game 4-43 is connected to the output terminal of the memory circuit 4-6.

The synchronous delay circuit 4-4 functions to delay the output of the synchronous delay circuit 4-3 or the memory circuit 4-6 in synchronization with the output pulse f0 from the pulse generating circuit 4-1, respectively.

The memory circuit 4-6 receives the data bus D0. It consists of a 2-pin memory 4-51 and 4-52 into which the data on D1 is written. Memory 4-
The output terminal of 61 is connected to the AND gate 4 in the gate circuit 4-2.
-23 is connected to the input end of the clock pulse φ. Memorizes high/low speed.

The output end of the memo IJ-4-52 is connected to the input end of the ant game 4-43 in the synchronous delay circuit 4-4, and stores 0N10FF of the clock 'ゞ'''φ.

Next, the operation of the above embodiment will be explained in order.

(1) When the CPU 1 writes the "o" value to the clock pulse 0N-OFF operation memory 4-62, the input of the AND gate 4-43 becomes "0" and its output becomes "0".
becomes. Since the pulse 4-42 reads this value, the output Q becomes "0". Therefore, the output φ of the AND game) 4-22 which takes this output Q as an input. is kept at a low level. That is, the output of the clock pulse generation circuit 4 is completely turned off.

When CPU1 writes the value "1" to memory 4-52, AN
One input of the D gate 4-43 becomes "1", and the output of the synchronous delay circuit 4-3 appears at the D input of the flip-flop circuit 4-42. If this is now set to "1", the output of the flip-flop circuit 4-4 becomes "1", making the AND gate 4-22 conductive and generating the clock pulse φ. appears.

(2) First operation of the clock pulse Based on the data indicating each access time stored in the memory 3 etc., the CPU 1 writes a "0" value to the memo voice +7-4-51, or the address decodes /From chip select signal generation circuit 2, AND
If the select signal CE given to Game) 4-23 is low level, that is, it is not selected, then AND Game) 4-
The output R of 23 is always at a low level. Therefore, the output pulse f0 from the pulse generation circuit 4-1 is directly applied to the output side of the ○R game) 4-21 to which this output is applied.
appears and is input to AND gate 4-22.

If the other input of the AND gate 4-22 is at a high level, that is, "1", this is the clock pulse φ. It is output as , and applied to CPU1.

That is, the gate circuit 4-2 is the clock pulse generating circuit 4-2.
The output f0 from 1 is output as is as a clock pulse f0, and a so-called fast operation is performed.

Looking at the synchronous delay circuit 4-3, the output R (low level) of the gate 4-23 (7) resets the counter 4-32 via the inverter 4-31, stopping the counting operation. Output A, B, C of counter 4-32
are all "0", so the NAND game that uses these as input) has a 4-330 output cover, and is al at high level. The conditions stated in the Clock Pulse ON-OFF operation section are now achieved.

(3) Slow operation of clock pulse The CPU 1 writes "1" to the memory 4-51 based on data indicating each access time stored in a specific address of the memory 3, etc.
After writing the value, the select signal from the address decoding/chip select signal generation circuit 2 goes from low level to high level, and when this is applied to the AND gate 4-23, a clock pulse φ is generated. The cycle becomes significantly longer and a slow operation is performed.

FIG. 2 shows a timing chart at this time.

In FIG. 2, A is the output pulse f0 from the pulse generating circuit 4-1, and B is the clock pulse φ. , C is the address generated by the CPU 1, D is the chip select signal CESE from the address decode/chip select signal generation circuit 2,
Are F and G counters? 4732 outputs A, B, C, H are N
The output of AND gate 4-33, ■ is the output of Noritsubu flop circuit 4-42, and ■ is the output R of AND gate 4-23.
, respectively indicate data on the data bus of the CPU 1.

In Figure 2, the memo IJ is currently operating at high speed.
The operation of writing low-speed data "1" to =4-51 and accessing the memory 3 at low speed will be described. As shown in the second diagram, the select signal CE from the address decode/chip select signal generation circuit 2 is r
Suppose that the value changes from OJ to "1". When the select signal GE changes from "0" to "1", the output R of the AND gate 4-23 changes from rOJ to "1" as shown in FIG. The output of becomes high level, and as shown in FIG. 2B, the clock pulse φ
. becomes high level. And AND gate 4-23
The output R is sent to the counter 4-2 via the inverter 4-31.
3, the counter 4-23 is reset and the output pulse f0 from the pulse generating circuit 4-1 is released.
count. Therefore, the output terminal A of the counter 4-23
, B, and C, outputs as shown in FIG. 2 E, F, and G appear, respectively. Then, at time T2, the counter 4-2
3 outputs A and B.

When all C become "1", the output EN of the NAND game (4-33) changes from "1" to "0" as shown in FIG. 2H. This change causes the output f0 from the pulse generation circuit 4-1 to change from "0" to "1" via the D flip-flop 4-42.
At the moment T3 changes to (AND game) 4-22.

Therefore, at this instant T3, the clock pulse φ.

changes from "1" to "o". Clock pulse φ. When changes from "1" to rOJ, the select signal CE changes from "1" to "0" by the action of CPU1, and the AND game)
The output R of 4-23 changes from "1" to "0". Therefore, in this state, the counter 4-32 is reset and outputs A.

If B and C are "0", they return. That is, at the timing of time T4, the counter 4-32 is reset and its output A
, B, and C return to "o". Therefore, NAND game)
The output EN of 4-33 changes from "O" to "1". This output is read by the flip-flop circuit 4-42 at time T6 and transmitted to the AND gate 4-22. At time T5, one input R of the OR gate 4-21 is rOJ, so the output f0 from the pulse generating circuit 4-1 appears as is at its output terminal. Since the output is applied to the AND gate 4-22, the output of the AND gate 4-22, that is, the clock pulse φ. As shown in FIG. 2B, the pulse generation circuit 4-
It becomes exactly the same as the output f0 from 1. That is, time T
The period of the clock pulse φ is extended only from 1 to T6, and thereafter returns to the original period. And in this case the clock pulse, φ. The leading edge period T when is at a high level, ~
T3 is a counter 4-3 in the first synchronous delay circuit 4-3
Period T3 of the trailing edge that is determined by the number of steps 2 and becomes low level
T6 is determined by the number of stages of the D flip-flop circuit 4-42 in the second synchronous delay circuit 4-4. Therefore, by arbitrarily selecting the number of these stages, the clock pulse φ. It is possible to arbitrarily set the period during the extension of , and during the extension of each of its leading and trailing edges.

As is clear from the above embodiments, the microcomputer device of the present invention is configured such that the clock pulse generation circuit supplies clock pulses with different periods to the central processing unit based on the data stored in the circuit in advance. Therefore, even if there are memories and peripheral devices with different access times, the data indicating the access time suitable for these memories and peripheral devices can be stored in the memory circuit in advance. This has the advantage that it is possible to obtain a microcomputer device that can access devices, has a high processing speed as a whole, and is extremely advantageous in terms of power consumption and cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a microcomputer device according to the present invention, and FIG. 2 is a diagram showing output waveforms of each part of the device. 1...Central processing unit, 2...Address decoding/chip select signal generation circuit, 3...
...Memory, 3-1...Specific address, 4.
...Cronk pulse generation circuit 1L4-1 ...Pahalus generation circuit, 4-11 ...Crystal oscillation circuit, 4-12 ...Branch circuit, 4-2・・・・・・
Gate circuit, 4-21...OR gate, 4-2
2.4-23-...and gate, 4-3...
... Synchronous delay circuit, 4-31 ... Inverter, 4-32 ... Counter"14-33 ...
...NAND gate, 4-4...Synchronous delay circuit, 4-41...Inverter, 4-42-...
...D flip-flop circuit, 4-6...memory circuit, 4-61, 4-62-...memory.

Claims (1)

[Claims] A clock pulse generation circuit, and a central processing unit driven by the output of the clock pulse generation circuit. Equipped with various memories and various peripheral devices, the clock pulse generation circuit is a pulse generation circuit, the pulsed data is decoded by the central processing unit, and the address decoder decodes the address signal from the central processing unit and outputs a chip select signal. / Consists of a memory circuit that stores data based on the select signal from the chip select signal generation circuit, and a synchronous delay circuit that receives the output of this memory circuit and the output of the pulse generation circuit as input, and controls the gate and circuit using the output. A microcomputer device configured such that the period of the output from the clock pulse generation circuit and the on/off state of the output are stored in advance in the memory circuit and can be specified based on the data.