JPS58129576U

JPS58129576U - Coin counting control device

Info

Publication number: JPS58129576U
Application number: JP2477882U
Authority: JP
Inventors: 牛島　義夫
Original assignee: 富士電機株式会社
Priority date: 1982-02-25
Filing date: 1982-02-25
Publication date: 1983-09-01

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来の硬貨計数制御装置を示す概略構成図、第
２図は本考案による硬貨計数制御装置の一実施例を示す
ブロック図、第３図Ａ＝Ｅ、第４図Ａ〜Ｅおよび第５図
Ａ〜Ｆのそれぞれは第２図に示す装置の動作を説明する
ための各部信号の波形図、第６図は本考案の別実施例を
示すブロック図、第７図Ａ〜１は第６図に示す装置の動
作を説明するための信号波形図、第８図は本考案の別実
゛−施例を示すブロック図、第９図Ａ〜Ｆは第８図に示
す装置の動作を説明するための信号波形図、第１０図は
本考案の別実施例を示すブロック図、第１１図は本考案
装置の動作をソフトウェア的に行う場合の動作制御を示
す流れ図である。１０．１１０・・・硬貨選別器、１１・・・硬貨通過孔
、１２Ａ、１２Ｂ、１２Ｇ・・・硬貨通路、１３Ａ。１３Ｂ、１３Ｇ・・・硬貨収納筒、１４Ａ、１４Ｂ。１４Ｃ・・・硬貨センサ、ｉ５Ａ、ｉ５Ｂ、１５Ｃ・・
・検知信号、１６，１６１．１６２・・・計数制御部、
２１．２１Ａ、２１Ｂ、２１Ｃ・・・硬貨投入センサ、
　　２２．２２Ａ、２２Ｂ、２２Ｃ・・・検知信号、２
３゜２３Ａ、２３Ｂ、２３Ｃ・・・計数記憶部、２４゜
１１１Ａ、ＩＩＩＢ、１ｌｌｃ・・・出力信号、２５゜
２９．６４，２５１・・・オアゲート、２６．　３０゜
６５・・・論理和出力信号、２７Ａ、２７Ｂ、２７Ｃ・
・・アンドゲート、２８Ａ、２８Ｂ、２８Ｃ・・・論理
和出力信号、６１・・・時分割回路、６２・・・クロッ
ク信号、６３Ａ、６３Ｂ、６３Ｃ・・・時分割出力信号
、１０１・・・タイマ。FIG. 1 is a schematic configuration diagram showing a conventional coin counting control device, FIG. 2 is a block diagram showing an embodiment of the coin counting control device according to the present invention, FIG. 3 A=E, FIGS. 4 A to E, and FIG. 5A to 5F are waveform diagrams of signals of various parts for explaining the operation of the device shown in FIG. 2, FIG. 6 is a block diagram showing another embodiment of the present invention, and FIGS. 7A to 1 are FIG. 6 is a signal waveform diagram for explaining the operation of the device shown in FIG. 6, FIG. 8 is a block diagram showing another embodiment of the present invention, and FIGS. 9 A to F are operation of the device shown in FIG. 8. FIG. 10 is a block diagram showing another embodiment of the present invention, and FIG. 11 is a flowchart showing operation control when the operation of the apparatus of the present invention is performed by software. 10.110... Coin sorter, 11... Coin passing hole, 12A, 12B, 12G... Coin passage, 13A. 13B, 13G... Coin storage tube, 14A, 14B. 14C...coin sensor, i5A, i5B, 15C...
・Detection signal, 16,161.162... counting control section,
21.21A, 21B, 21C... coin insertion sensor,
22.22A, 22B, 22C...detection signal, 2
3゜23A, 23B, 23C... Count storage section, 24゜111A, IIIB, 1llc... Output signal, 25゜29.64, 251... OR gate, 26. 30°65...OR output signal, 27A, 27B, 27C.
...AND gate, 28A, 28B, 28C...OR output signal, 61...Time division circuit, 62...Clock signal, 63A, 63B, 63C...Time division output signal, 101... timer.

Claims

[Scope of utility model registration request]

(1) A coin insertion sensor that detects that a coin is inserted into the coin sorter, and an insertion storage section that sequentially stores and holds insertion detection signals generated by the coin insertion sensor, and is arranged separately from the coin insertion sensor. a coin sensor for each denomination, an output control unit that outputs a counting signal when the coin sensor detects a coin when the insertion detection signal is stored in the input storage unit, and a counting signal of the output control unit. 1. A coin counting control device, comprising: a coin counting control section that calculates an input amount based on a signal, and wherein the stage-large storage section sequentially cancels memory retention based on a counting signal from the output control section.

(2) Utility Model Registration Scope of the Claims In the coin counting control device according to claim 1, the output control section has the output of the counting storage section as one input, and the output of the detection signal from the coin sensor as the other input. A coin counting control device comprising a logic circuit.

(3) Utility Model Registration The coin counting control device according to claim 1, wherein the input storage section is a reversible counting circuit.