JPS58127344A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS58127344A
JPS58127344A JP1036982A JP1036982A JPS58127344A JP S58127344 A JPS58127344 A JP S58127344A JP 1036982 A JP1036982 A JP 1036982A JP 1036982 A JP1036982 A JP 1036982A JP S58127344 A JPS58127344 A JP S58127344A
Authority
JP
Japan
Prior art keywords
width
oxide film
silicon oxide
groove
oxidation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1036982A
Other languages
Japanese (ja)
Inventor
Toshiaki Ogata
尾形　俊昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP1036982A priority Critical patent/JPS58127344A/en
Publication of JPS58127344A publication Critical patent/JPS58127344A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers

Abstract

PURPOSE:To realize high integration density of an MOS semiconductor device by narrowing the width of element separation region. CONSTITUTION:A large groove having the width 8 of aperture which is made smaller than the depth 9 is formed in rectangular or in the form similar to rectangular by the reactive ion etching. The numeral 10 is a mask material such as photo resists. The groove formed on a silicon substrate is filled with a silicon oxide film 11 in the thermal oxidation process. When an oxidation mask material is composed of an alumina film, the anode oxidation method is used. In the method of this invention, since the silicon oxide film filling the groove is almost satisfied by oxidation in both sides of groove since the depth 9 of groove formed on the silicon substrate is made larger than the width 8 of the aperture. Therefore, since the oxidation time for forming a silicon oxide film for element separation can be sufficiently curtailed, generation of bird's beak is very rare even in case the silicon oxide film is formed as a buffer. For example, in case the width of aperture is 0.3mum, the width of element separation region can be set to 0.6mum or less. This value is negligibly small.

Description

【発明の詳細な説明】 本発明は、Ｍ（１ｍｌ半導体装置の秦子会ｉｌｌ形成工
程に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a process for forming a 1ml semiconductor device.

本発ｇＡの目的は％ＭＯｉ１ｍｌ半導体装置の高集積化
を実現する為に素子分離に要する面積を極限まで小さく
する事に有る。The purpose of this invention is to minimize the area required for element isolation in order to achieve high integration of a %MOi 1 ml semiconductor device.

以下図に依って詳しく説明する。This will be explained in detail below with reference to the figures.

第１ｍは従来の製造方法による素子分離を示す図である
。シリコン基板１上に薄い緩衝用の酸化シリ；ン膜を形
成するか、あるいは直接に窒化シリコン膜２を形成し、
窒化シリコンｊｌ［２を酸化マスクとしてシリコン基板
１を選択的に酸化し、酸化シリコンＨｓを形成する０図
の４はイオン注入によるストッパ拡散層を示す。館１図
に示す従来の素子分離法では窒化シリコン膜のフォトエ
ツチング可能な最小線巾が１３μ慣であってもバーズビ
ーク５の発生によって１μ％程度の巾が嵌子分離領域と
して必要になる。1m is a diagram showing element isolation by a conventional manufacturing method. A thin silicon oxide film for buffering is formed on the silicon substrate 1, or a silicon nitride film 2 is directly formed.
The silicon substrate 1 is selectively oxidized using the silicon nitride jl[2 as an oxidation mask to form silicon oxide Hs. 4 in FIG. 4 shows a stopper diffusion layer formed by ion implantation. In the conventional device isolation method shown in FIG. 1, even if the minimum photoetchable line width of the silicon nitride film is 13 μm, a width of about 1 μ% is required as the insert separation region due to the occurrence of bird's beak 5.

本発明は上記の欠点を除来して素子分離領域の巾を小さ
くしてＭＯ５１ｍｌ半導体装置の高集積化を実現するも
のである。第２図、第３図、第４図に本発明の製造方法
を示す。ｊＩ２図に示す様にシリコン基板６上に直接も
しくは緩衝用の酸化シリコン膜を介して窒化シリコン膜
もしくはアルミナ膜７を形成する。次いで第３図に示す
様に窒化シリコン膜７をエツチングし、同時にシリ；ン
基板ニ開口部の巾８より深さ９０大きい溝を反応性イオ
ンエツチング等で矩形もしくはそれに近い形で形成する
。図の１０はフォトレジスト等のマスク材を示す。シリ
コン基板に形成された溝は熱酸化工程によって第４図に
示す様に酸化シリコンＪ［１１で充たされる。酸化マス
ク材がアルミナ膜の場合には陽極酸化法を用いる事が出
来る０本発明の製造方法ではシリコン基板に形成する溝
の深さ９を開口部の巾８より大きくするので、溝を充た
す酸化シリコン膜はほとんど溝の両側面の酸化で充足さ
れる。従って素子分離の酸化シリコン膜を形成する酸化
時間が従来の製造方法に比べて充分短く出来るので酸化
シリコン膜を緩衝用に形成した場合にもバーズビークの
発生は極めて小さい０例えば開口部の巾がｌｌｓμ集の
場合素子分離領域の巾は１６μ愕以下に出来る。この値
は５１１図の従来の製造方法の場合と比較して充分小さ
い値である。また表面をほぼ平担に出来る点も特長であ
る。The present invention eliminates the above-mentioned drawbacks, reduces the width of the element isolation region, and realizes a highly integrated MO51ml semiconductor device. The manufacturing method of the present invention is shown in FIGS. 2, 3, and 4. As shown in FIG. jI2, a silicon nitride film or an alumina film 7 is formed directly on a silicon substrate 6 or via a silicon oxide film for buffering. Next, as shown in FIG. 3, the silicon nitride film 7 is etched, and at the same time, a trench having a depth 90 greater than the width 8 of the opening in the silicon substrate is formed by reactive ion etching or the like in a rectangular or nearly rectangular shape. 10 in the figure indicates a mask material such as photoresist. The groove formed in the silicon substrate is filled with silicon oxide J[11] by a thermal oxidation process, as shown in FIG. When the oxidation mask material is an alumina film, an anodic oxidation method can be used.In the manufacturing method of the present invention, the depth 9 of the groove formed in the silicon substrate is made larger than the width 8 of the opening, so the oxidation method filling the groove is The silicon film is mostly filled with oxidation on both sides of the trench. Therefore, since the oxidation time for forming the silicon oxide film for element isolation can be sufficiently shortened compared to the conventional manufacturing method, the occurrence of bird's beak is extremely small even when the silicon oxide film is formed for buffering. In the case of a multilayer device, the width of the element isolation region can be reduced to 16 μm or less. This value is sufficiently small compared to the case of the conventional manufacturing method shown in FIG. 511. Another feature is that the surface can be made almost flat.

図の１２はイオン注入によるストッパ拡散層を示す。12 in the figure shows a stopper diffusion layer formed by ion implantation.

本発明の半導体装置の製造方法は素子分離領域を非常に
小さく出来かつ表面が平担であるので電子ビーム露光法
、Ｘ線露光法等で形成されるサブミクロン素子を有する
半導体装置の製造方法としている。Since the method for manufacturing a semiconductor device of the present invention can make the element isolation region extremely small and has a flat surface, it can be used as a method for manufacturing a semiconductor device having submicron elements formed by electron beam exposure, X-ray exposure, etc. There is.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の製造方法による素子分離を示す図である
。 第２ｖＡ、第３図、第４図は本発明の製造方法の素子分
離を示す図である。 １、Ｓ−・・・・・シリコン基板 ２・・・・・・・・・・・・窒化シリコン属３．１１・
・・酸化シリコン膜 ５・・・・・・・・・・・・バーズビーク７・・・・・
・川・・・窒化シリコン膜もしくはアルミナ膜８・・・
・・・・・・・・・溝の巾 ９・・・・・・・・・・・・溝の深さFIG. 1 is a diagram showing element isolation by a conventional manufacturing method. 2vA, FIG. 3, and FIG. 4 are diagrams showing element isolation in the manufacturing method of the present invention. 1, S-...Silicon substrate 2...Silicon nitride 3.11.
...Silicon oxide film 5...Bird's beak 7...
・River...Silicon nitride film or alumina film 8...
・・・・・・・・・Groove width 9・・・・・・・・・Groove depth

Claims (1)

【特許請求の範囲】[Claims] 窒化シリコン膜もしくはアルミナ膜を形成する工程と、
該窒化シリコン膜もしくはアルミナ膜をフォトエツチン
グすると共にシリコン基板にＮ０部の巾より深い矩形の
溝を形成する工程と、該シリコン基板を選択酸化し、該
矩形の溝を酸化膜で充たす工程管有する事を特徴とする
半導体装置の製造方法。A step of forming a silicon nitride film or an alumina film,
A process tube includes a process of photoetching the silicon nitride film or alumina film and forming a rectangular groove deeper than the width of the N0 part in the silicon substrate, and selectively oxidizing the silicon substrate and filling the rectangular groove with an oxide film. A method for manufacturing a semiconductor device characterized by:
JP1036982A 1982-01-26 1982-01-26 Preparation of semiconductor device Pending JPS58127344A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1036982A JPS58127344A (en) 1982-01-26 1982-01-26 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1036982A JPS58127344A (en) 1982-01-26 1982-01-26 Preparation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS58127344A true JPS58127344A (en) 1983-07-29

Family

ID=11748237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1036982A Pending JPS58127344A (en) 1982-01-26 1982-01-26 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS58127344A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH021916A (en) * 1988-06-10 1990-01-08 Mitsubishi Electric Corp Formation of isolated oxide film
US5696021A (en) * 1993-08-31 1997-12-09 Sgs-Thomson Microelectronics, Inc. Method of making a field oxide isolation structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5388584A (en) * 1977-01-17 1978-08-04 Hitachi Ltd Production of sio2 layer for interelement isolation
JPS56130940A (en) * 1980-03-17 1981-10-14 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5388584A (en) * 1977-01-17 1978-08-04 Hitachi Ltd Production of sio2 layer for interelement isolation
JPS56130940A (en) * 1980-03-17 1981-10-14 Fujitsu Ltd Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH021916A (en) * 1988-06-10 1990-01-08 Mitsubishi Electric Corp Formation of isolated oxide film
US5696021A (en) * 1993-08-31 1997-12-09 Sgs-Thomson Microelectronics, Inc. Method of making a field oxide isolation structure

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