JPS58125971A - Solid-state image pickup element - Google Patents

Solid-state image pickup element

Info

Publication number
JPS58125971A
JPS58125971A JP57008444A JP844482A JPS58125971A JP S58125971 A JPS58125971 A JP S58125971A JP 57008444 A JP57008444 A JP 57008444A JP 844482 A JP844482 A JP 844482A JP S58125971 A JPS58125971 A JP S58125971A
Authority
JP
Japan
Prior art keywords
group
photoelectric conversion
substrate
layer
vertical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57008444A
Other languages
Japanese (ja)
Inventor
Hiroshi Tanigawa
紘 谷川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57008444A priority Critical patent/JPS58125971A/en
Publication of JPS58125971A publication Critical patent/JPS58125971A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14643Photodiode arrays; MOS imagers

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

PURPOSE:To stabilize the black level, by locating the buried layers in separating each other which are formed at the lower part of each photoelectric converting element group and vertical element group, and at the same time forming a light shielding means at the upper part of an intermediate region. CONSTITUTION:A buried layer 50 of conduction type opposite to a substrate 10 is formed within the substrate 10 provided at the lower part of an area between a diffusion layer 40 forming a light-shielded photoelectric converting element and a vertical register region contiguous with the layer 40. At the same time, a buried layer 51 of conduction type opposite to the substrate 10 is formed within the substrate provided at the lower part of an area between a photoelectric element group 11 and a vertical register group 53 contiguous with the element 11. These layers 50 and 51 are separated from each other, and a high-density region 42 of conduction type same as the substrate 10 is provided between the layers 50 and 51. In such a constitution, the incident light containing near ultraviolet rays is absorbed by a depeletion layer of pn junction formed with the inside of the buried layer of the layer 51, the layer 51 and the substrate 10 and converted into the electric charge. As a result, a factor which induces the fluctuation of black level is deleted.

Description

【発明の詳細な説明】 本発明は半導体基板上に複数の光電変換素子群が設けら
れた固体撮像素子に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state image sensor in which a plurality of photoelectric conversion element groups are provided on a semiconductor substrate.

近年の半導体・集積回路技術の急速な発達を背景にして
固体撮像素子の開発が強力に推進されてきた。固体撮像
素子では画素の走査を電子的に行ない、かつ1画素配列
が写真蝕刻技術を用いて高精度に決定されるため、被写
体操像時の画像歪が発生しにくい利点があり、撮像管の
代替として製品化が期待されている。家庭用VTRのテ
レビカメラとしての応用公費に限定するならば、十分な
画素数で十分な再生画像を提供する固体撮像素子が実用
化されつつある。しかしながら、局用テレビカメラある
いは情報処理端末としてのテレビカメラを想定するなら
ば、末だ十分な性能を有する素子は開発されていない。
With the rapid development of semiconductor and integrated circuit technology in recent years, the development of solid-state image sensors has been strongly promoted. In solid-state imaging devices, pixels are scanned electronically, and the pixel arrangement is determined with high precision using photolithographic technology, so it has the advantage that image distortion is less likely to occur when imaging a subject, and the imaging tube It is expected that it will be commercialized as an alternative. If the application is limited to public funds for use as a television camera for home VTRs, solid-state image pickup devices that provide sufficient reproduced images with a sufficient number of pixels are being put into practical use. However, if we assume a television camera for a station or a television camera as an information processing terminal, no element with sufficient performance has been developed.

第1図は従来の固体撮像素子の構造を説明する概略構成
図であり、インターライン型固体操像素子と称される素
子である。同図においては説明の便宜上(3X3)の画
素を有する素子が示されている。同図において1は光電
変換素子、2は垂直レジスタ、3は水平レジスタ、4は
出力回路、5は出力端子である。インターライン型固体
操像素子は広く周知であるので動作の詳細は省略して、
概要のみを記述する。−垂直走査周期(フィールドある
いはフレーム)で光電変換された信号電荷は垂直ブラン
キング期間内で垂直レジスタ2の各対応する位蓋に、並
列的に移動する。第1図においては、光電変換素子1と
垂直レジスタ2との中間に設−置された前記移動を制御
する転送ゲート電極および、所望の移動が達成されるよ
うなチャネルストッパ等が省略されている。垂直レジス
タ2へ並列的に移動した信号電荷は、−水平走査周期毎
に下方へ順次移動する。一方、水平レジスタ3は水平ブ
ランキング期間内に前記垂直レジスタ2より信号電荷を
受は取り、第1図の左方向へ順次移動させる。この移動
により出力回路4に達した信号電荷は順次電圧信号に変
換され、出力端子5を介して時系列画信号が出力される
。第1図のレジスタ2,3は電荷結合素子、あるいはバ
ケツリレー素子で構成されているアナログシフトレジス
タである。かかる動作に従って、−垂直走査周期かかっ
て前記信号電荷が全て読み出されている開光電変換素子
1は入射光量に応じた電荷量を蓄積することになる。−
垂直周期終了時刻に再び光電変換素子1から垂直レジス
タ2への信号電荷の移動が達成される。このインターラ
イン型素子は、光電変換素子群とレジスタ群とが空間的
に多重化されているため、チップ面を積が小さくなり歩
留まり向上、低価格化が期待できる。しかし、固体撮像
素子では、動作温度上昇に伴ない、暗電流が増大し、入
射光が無−い時の出力電圧が増大することが知られてい
る。当該素子をシリコンで作成するならば、10℃の温
度上昇で、暗電流は大略2倍に増大する。通常のシリコ
ン集積回路が0℃から70℃の温度範囲での動作を保証
していることを考慮すれば、当該素子も当該温度範囲で
の正常動作が要求される。しかるに、前述した関係を用
いるならば、70℃での暗電流線θ℃における暗電流よ
りも約100倍に達するため、電気的な信号処理により
、当該暗電流を自動補正しなければ、蚊素子の実用は期
しがたい。より簡便に、かかる暗電流を補正するために
控、所謝オプティカルブラックを該素子内に設けるのが
良い。該オプティカルブラックは該素子内の垂直方向に
配列された一列ないしは複数列の光電変換素子を不透明
膜で遮光することにより得られる。第1図の例において
は、右側の一列を構成する第一の該光電変換素子群7,
8.9がオプティカルブラックとして例示されている。
FIG. 1 is a schematic diagram illustrating the structure of a conventional solid-state image sensor, which is called an interline solid-state image sensor. In the figure, for convenience of explanation, an element having (3×3) pixels is shown. In the figure, 1 is a photoelectric conversion element, 2 is a vertical register, 3 is a horizontal register, 4 is an output circuit, and 5 is an output terminal. Since the interline solid-state image element is widely known, details of its operation will be omitted.
Write only an overview. - Signal charges photoelectrically converted in a vertical scanning period (field or frame) are moved in parallel to corresponding positions of the vertical register 2 within a vertical blanking period. In FIG. 1, the transfer gate electrode installed between the photoelectric conversion element 1 and the vertical register 2 to control the movement, and the channel stopper to achieve the desired movement are omitted. . The signal charges that have been moved in parallel to the vertical register 2 are sequentially moved downward every -horizontal scanning period. On the other hand, the horizontal register 3 receives and removes signal charges from the vertical register 2 during the horizontal blanking period, and sequentially moves them to the left in FIG. The signal charges reaching the output circuit 4 due to this movement are sequentially converted into voltage signals, and a time-series image signal is outputted via the output terminal 5. Registers 2 and 3 in FIG. 1 are analog shift registers composed of charge-coupled devices or bucket brigade devices. According to this operation, the photoelectric conversion element 1, from which all the signal charges have been read out over a -vertical scanning period, accumulates an amount of charge corresponding to the amount of incident light. −
At the end of the vertical cycle, the signal charges are transferred from the photoelectric conversion element 1 to the vertical register 2 again. In this interline type element, since the photoelectric conversion element group and the register group are spatially multiplexed, the area of the chip surface is reduced, and an improvement in yield and a reduction in price can be expected. However, it is known that in solid-state imaging devices, as the operating temperature increases, the dark current increases and the output voltage when there is no incident light increases. If the device is made of silicon, a 10° C. temperature increase will approximately double the dark current. Considering that normal silicon integrated circuits are guaranteed to operate within a temperature range of 0° C. to 70° C., the device is also required to operate normally within this temperature range. However, if we use the above-mentioned relationship, the dark current line at 70°C is about 100 times higher than the dark current at θ°C, so unless the dark current is automatically corrected by electrical signal processing, the mosquito element It is difficult to expect that it will be put into practical use. To make it easier to correct such dark current, it is preferable to provide an optical black in the element. The optical black can be obtained by shielding one or more rows of photoelectric conversion elements vertically arranged in the element with an opaque film. In the example of FIG. 1, the first photoelectric conversion element group 7 constituting the row on the right side,
8.9 is exemplified as optical black.

また、2で例示される垂直レジスタ群上には光遮蔽のた
めの不透明膜を配置しない限り、信号電荷を垂直方向に
移動させている期間(即ち垂直走査期間になる)に入射
光により発生した電荷が前記信号電荷に付加されるため
、スミアと呼ばれる白線が再生画像に現われ、画質を極
度に劣化させることが知られている。かかる理由により
、不透明膜がレジスタ群上に配列されなければならない
。通常不透明膜はアルミニウム等の金属電極で構成され
ている 第2図は第1図に示したA−A’部の構造断面
図を示している。なお同図では、説明の便宜上、概念的
な構造断面図が示されているに過ぎず、寸法的に社実際
の素子と必らずしも対応しているとは限らない。同図に
おいて10は第一の導電型(例えばp型)の半導体基板
、11は第二の導電型(例えばn型)の拡散層で、基板
10との間にp−n接合を形成し、光電変換索子lを構
成している。12は垂直レジスタ2を構成する一つの転
送電極、13は前述した転送ゲート電極、14および1
4/は前記不透明膜、15はチャネルストッパである。
In addition, unless an opaque film for light shielding is placed on the vertical register group as exemplified in 2, the signal charges generated by the incident light during the period when the signal charges are moving in the vertical direction (that is, the vertical scanning period) It is known that since charges are added to the signal charges, a white line called smear appears in the reproduced image, severely degrading the image quality. For this reason, an opaque film must be arranged over the registers. Usually, the opaque film is composed of a metal electrode such as aluminum. FIG. 2 shows a structural cross-sectional view of the section AA' shown in FIG. Note that this figure merely shows a conceptual cross-sectional view of the structure for convenience of explanation, and does not necessarily correspond to the actual element in terms of dimensions. In the figure, 10 is a semiconductor substrate of a first conductivity type (e.g., p-type), 11 is a diffusion layer of a second conductivity type (e.g., n-type), which forms a p-n junction with the substrate 10, It constitutes a photoelectric conversion cable l. 12 is one transfer electrode constituting the vertical register 2, 13 is the aforementioned transfer gate electrode, 14 and 1
4/ is the opaque film, and 15 is a channel stopper.

転送電極12、ゲート電極13は図示されていない絶縁
膜を介して基板10上に配置され、さらに、不透明膜1
4゜14′は電極12.13とも絶縁膜を介して配置さ
れている。チャネルストッパ15は、拡散層11内に蓄
積された信号電荷がゲート電極13の下を経由して転送
電極12の下へ一方向に移動させるために設けられてお
り、該信号電荷に対しては電位障壁として作用する。ま
た、16は8の上部に設けられた、遮光用の不透明膜で
ある。当骸膜16は14と同一になるよう構成すること
もできるし第2図の構造物の表面に設けられた図示され
ていない樹脂層の16に相当する領域のみを染色あるい
は蒸着膜等により透過率を減せしめても良い。
The transfer electrode 12 and the gate electrode 13 are arranged on the substrate 10 via an insulating film (not shown), and the opaque film 1
4.degree. 14' is also arranged with the electrodes 12 and 13 through an insulating film. The channel stopper 15 is provided in order to move the signal charges accumulated in the diffusion layer 11 in one direction under the transfer electrode 12 via the gate electrode 13. Acts as a potential barrier. Moreover, 16 is an opaque film for light shielding provided on the upper part of 8. The shell film 16 can be configured to be the same as 14, or only the area corresponding to 16 of the resin layer (not shown) provided on the surface of the structure shown in FIG. It is also possible to reduce the rate.

前述した当該素子の動作に従えば、−水平走査周期の終
了周期において、16が被着された7、8゜9からの信
号が得られる。当該信号は前述した暗電流成分のみであ
り、入射光により発生した電荷祉含まれていないので、
当該信号のレベルを真の黒レベル、即ち、黒の基準信号
とみなし、5から得られる信号を交流増幅する際に、ク
ランプ回路を用いて黒信号レベルを直流再生することが
できる。当該信号処理によれば、該素子の動作温度が上
昇しても、暗電流に起因する信号レベルの浮動が阻止で
き、自動的に安定した画像信号が得られる。以上の説明
では、オプティカルブラックを当該素子の右側−列のみ
の場合を例示したが、一般的には、互いに隣接する複数
列をオプティカルブラックにしたり、当該素子の左側の
部分に該オプティカルブラック領域を設けたりすること
が行なわれる。かかる従来例においては、該オプティカ
ルブラック構造により、大略真の黒レベルが得られるこ
とが知られている。しかしながら、入射光量が極度に多
くなったり、入射光に近赤外光が多分に含まれている場
合には、想定した真の黒レベルが白レベル方向に変動す
る欠点が存在した。かかる変動の要因の一つは近赤外光
により基板10の深部で発生した電荷が拡散により16
直下の光電変換素子に蓄積されることである。かかる変
動は撮像画像に横縞が発生したり、黒レベルの浮上りに
より画面全体が白っぽくなる等の悪影響を与え、画質の
極度な劣化を引き起こす。特に業務用に用いられる固体
撮像素子では1.かかる黒レベルの変動のため、応用分
野が狭められることになる。
According to the operation of the element as described above, at the end of the -horizontal scanning period, a signal is obtained from 7,8°9 on which 16 was deposited. The signal contains only the dark current component mentioned above and does not include the charge generated by the incident light.
The level of this signal is regarded as a true black level, that is, a black reference signal, and when the signal obtained from 5 is amplified by AC, the black signal level can be reproduced by DC using a clamp circuit. According to the signal processing, even if the operating temperature of the element increases, fluctuations in the signal level due to dark current can be prevented, and a stable image signal can be automatically obtained. In the above explanation, the case where optical black is applied only to the right column of the element is illustrated, but in general, multiple adjacent columns are optically black, or the optical black area is applied to the left side of the element. There will be things like setting things up. In such a conventional example, it is known that a substantially true black level can be obtained by the optical black structure. However, when the amount of incident light becomes extremely large or when the incident light contains a large amount of near-infrared light, there is a drawback that the assumed true black level fluctuates toward the white level. One of the causes of such fluctuations is that charges generated deep in the substrate 10 due to near-infrared light are diffused into 16
It is accumulated in the photoelectric conversion element directly below. Such fluctuations have adverse effects such as horizontal stripes appearing in the captured image and the entire screen becoming whitish due to a raised black level, resulting in extreme deterioration of image quality. Especially in solid-state image sensors used for professional use, 1. Such variations in black level narrow the field of application.

本発明の目的は、かかる従来の欠点を排除し、黒レベル
の安定化を計った固体撮像素子を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate such conventional drawbacks and provide a solid-state image sensor that stabilizes the black level.

本発明によれば一導電型を有する半導体基板上に形成さ
れた複数の光電変換素子群と、複数列の埋め込みチャネ
ル構造の垂直レジスタ群と、該垂直レジスタ群の一端に
隣接して設けられた水平レジスタと、該水平レジスタの
一端に設けられた出力回路と、前記光電変換素子群から
前記垂直レジスタへ周期的に信号電荷を移動せしめる手
段と、該光電変換素子群の端部に位置する第一の当該光
電変換素子群の上部に設けられた遮光手段とを有するイ
ンターライン型固体撮像素子において、前記第一〇光電
変換素子群と該素子群に隣接して設けられた第一の前記
垂直レジスタ群との下部に形成された前記基板どは反対
導電型の第一の埋め込み層と、約記第−の光電変換素子
群を含まない第二の前記光電変換素子群と該第二の素子
群に隣接して設けられた第二の前記垂直レジスタ群との
下部に形成された前記基板とは反対導電型の第二の埋め
込み層とが互いに分離して配置され、該第−と第二の埋
め込み層との中間領域の上部に遮光手段が設けられたこ
とを特徴とする固体撮像素子が得られる。
According to the present invention, a plurality of photoelectric conversion element groups formed on a semiconductor substrate having one conductivity type, a vertical resistor group having a buried channel structure in multiple rows, and a vertical resistor group provided adjacent to one end of the vertical resistor group a horizontal register, an output circuit provided at one end of the horizontal register, a means for periodically moving signal charges from the photoelectric conversion element group to the vertical register, and a means for periodically transferring signal charges from the photoelectric conversion element group to the vertical register; In an interline solid-state image sensor having a light shielding means provided on the upper part of the photoelectric conversion element group, the first photoelectric conversion element group and the first vertical light shielding means provided adjacent to the element group. The substrate formed under the resistor group includes a first buried layer of an opposite conductivity type, a second photoelectric conversion element group that does not include the second photoelectric conversion element group, and the second element. a second buried layer of a conductivity type opposite to that of the substrate formed below the second vertical resistor group provided adjacent to the vertical register group; A solid-state imaging device is obtained, characterized in that a light shielding means is provided above an intermediate region between the buried layer and the buried layer.

次に本発明について実施例を挙げて詳細な説明を行なう
Next, the present invention will be described in detail with reference to examples.

第3図は本発明の一実施例の断面図である。同図は第2
図に対応して描かれており、1g2図と同一番号は同一
構成要素を示している。本実施例では垂直レジスタ、水
平レジスタが共に埋め込みチャネル構造を採用している
場合である。同図において、40は前述した第一の光電
変換素子群の一つである8を構成する拡散層、50.5
1は1゜と反対導電型の埋め込み層であり、前記關−の
光電変換素子群の−っである8と、該素子に1iil接
して設けられた第一の前記垂直レジスタ群の一つである
互」との下部で該基板lo内に設けられた第一の埋め込
み層である50と、該第−〇光電変換素子群を含まない
第二の前記光電変換素子群の一つ例えば11と、該素子
に隣接して設けられた第二の前記垂直レジスタ群の−っ
である53との下部で該基板10内に設けられた第二の
埋め込み層である51とに分離されている。本実施例で
は埋め込みチャネル構造を採用しているので、11゜4
0は50.51と反対導電型、即ち、10と同一導電型
、15は51と同一導電型、即ち、10と反対導電型と
なるよう選択される。42は10と同一導電型を有する
高濃度領域である。かかる構成を採用すれば、前述した
従来例における黒レベルの変動を誘起する要因を有効に
、かつ、容易に除去できることが次に示される。近赤外
光を含む入射光は51の埋込み層内部、および、51と
10とが形成するpn接合の空乏層内で吸収され電荷に
変換されるよう咳接合の深さが予め設定されている。か
かる素子構造と入射光の吸収との関連については周知で
あるので具体的な設計法については省略する。なお、実
際の当該素子の応用では波長1μm以上の近赤外光につ
いては不要であるため、当該素子・上部に設けられた赤
外遮断光学フィルタにより除外されることが多い。かか
る理由により、空乏化されていないような10の領域で
電荷が発生することは無い。一方、51と50の端部で
は、それぞれ54.55で例示するが如き電界が作用す
るため、51の領域で発生した電荷が50の領域へ達し
、40に蓄積されたり%秤にもれこむことは無い。かか
る説明により1本実施例によれば強い入射光が存在する
時に黒レベルの変動が阻止できることが理解された。な
お1本実施例では、42が15よりも幅が大きいため、
水平レジスタ3の42に対向する部分に対応して該レジ
スタの構成素子数を増大させることが必要となる。かか
る構成素子数の増大は、該レジスタを駆動するドライバ
での消費電力を増大させることになるが、該素子数の増
大の率は数%以下であるため、重要な問題とはなり得な
い。また、42は前記50.51の中間領域に設けられ
ており、54.55の電界が実現するよう、即ち、50
゜51とが当該断面内では電気的に分離されるよう作用
するものであり、42の端部は50.51と接触してい
ても良く、また、420幅は設計上適宜選択されるもの
とする。さらに、50.51とが当該断面内において電
気的に分離されるならば42は必らずしも必要とは限ら
ず、省略することによりプロセス工程を簡略化すること
もできる。
FIG. 3 is a sectional view of one embodiment of the present invention. The same figure is the second
The same numbers as those in Figure 1g2 indicate the same components. In this embodiment, both the vertical register and the horizontal register employ a buried channel structure. In the figure, reference numeral 40 denotes a diffusion layer constituting 8, which is one of the first photoelectric conversion element groups, and 50.5
1 is a buried layer of conductivity type opposite to that of 1°, and 8 is one of the adjacent photoelectric conversion element groups, and one of the first vertical resistor groups provided in contact with the element. 50, which is a first buried layer provided in the substrate lo at the lower part of a certain mutually spaced area, and one of the second photoelectric conversion element groups that does not include the photoelectric conversion element group No. 0, for example, 11. , a second vertical resistor group 53 provided adjacent to the device, and a second buried layer 51 provided in the substrate 10 below. In this example, since a buried channel structure is adopted, the angle of 11°4
0 is selected to be the opposite conductivity type to 50.51, ie, the same conductivity type as 10, and 15 is selected to be the same conductivity type as 51, ie, the opposite conductivity type to 10. 42 is a high concentration region having the same conductivity type as 10; It will be shown next that if such a configuration is adopted, the factors that induce variations in the black level in the conventional example described above can be effectively and easily removed. The depth of the junction is set in advance so that the incident light including near-infrared light is absorbed inside the buried layer 51 and the depletion layer of the pn junction formed by 51 and 10 and converted into electric charge. . Since the relationship between such element structure and absorption of incident light is well known, a detailed description of the design method will be omitted. Note that in actual applications of the device, near-infrared light with a wavelength of 1 μm or more is unnecessary, so it is often excluded by an infrared cutoff optical filter provided on the top of the device. For this reason, charges are not generated in the 10 regions that are not depleted. On the other hand, at the ends of 51 and 50, an electric field as exemplified by 54.55 acts, so the charges generated in the area of 51 reach the area of 50 and are accumulated in 40 or leak into the % scale. There's nothing wrong with that. From this explanation, it was understood that according to this embodiment, fluctuations in the black level can be prevented when strong incident light is present. Note that in this embodiment, 42 is wider than 15, so
It is necessary to increase the number of constituent elements of the horizontal register 3 corresponding to the portion facing 42. Such an increase in the number of constituent elements will increase power consumption in the driver that drives the register, but since the rate of increase in the number of elements is less than a few percent, this cannot be a significant problem. Further, 42 is provided in the intermediate region of 50.51, so that an electric field of 54.55 is realized, that is, 50.
゜51 acts to be electrically isolated within the cross section, the end of 42 may be in contact with 50.51, and the width of 420 shall be selected as appropriate in the design. do. Further, if 50 and 51 are electrically isolated within the cross section, 42 is not necessarily necessary, and the process steps can be simplified by omitting it.

42の上部に設けられた不透明膜14は基板10内の4
2の領域内で入射光により発生した電荷が55の電界に
より50内へ引き込まれないようにするため必要である
。しかしながら42の上部に設けられた当該不透明膜は
、第3図においては14が延長されて配置される場合が
示されているが、これに限らず、16が同図における左
側方向に延長されるような構成法であっても構わない。
Opaque film 14 provided on top of 42 in substrate 10
This is necessary to prevent charges generated by the incident light in the region 2 from being drawn into the area 50 by the electric field 55. However, although the opaque film provided on the upper part of 42 is shown in FIG. 3 in which 14 is extended, the present invention is not limited to this, and 16 is extended in the left direction in the figure. Any configuration method may be used.

以上、本発明について実施例を挙げ、詳細な説明を行っ
た。本明細書では説明の便宜上、オプティカルブラック
が当該素子の右側−列の場合についてのみ例示した′が
、左側にあっても良く、また両側にあっても良く、さら
に、互いに隣接する複数列あっても良い。なお、16の
遮光膜の実現手段については、14.14’と同一ある
いは同様な工程、例えばアルミ等の金属蒸着膜による方
法に限らず、該遮光膜を当該素子表面上に密着あるいは
近接して設けられた樹脂あるいはガラスの透過率を減少
させることにより実現することも本発明に含まれる。ま
た、本発明は単にインターライン型固体撮像素子に限定
されることなく、他の固体撮像素子、例えば、フレーム
転送型固体撮像素子等にも広く応用することができる。
The present invention has been described above in detail using examples. In this specification, for convenience of explanation, the case where the optical black is on the right side of the element is illustrated, but it may be on the left side or on both sides, and furthermore, there may be multiple adjacent columns. Also good. Note that the means for realizing the light-shielding film in 16 is not limited to the same or similar process as in 14.14', for example, the method using a metal vapor deposition film such as aluminum, but also the method by which the light-shielding film is brought into close contact with or in close proximity to the surface of the element. The present invention also includes realization by reducing the transmittance of the resin or glass provided. Further, the present invention is not limited to an interline type solid-state image sensor, but can be widely applied to other solid-state image sensors, such as a frame transfer type solid-state image sensor.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はインターライン型固体撮像素子の概念的な構造
平面図、第2図・はそのA−A’断面図、第3図は本発
明の実施例を示す概念的な構造断面図である。 1・・・・・・光電変換素子、2・・・・・・垂直レジ
スタ、3・・・・・・水平レジスタ、4・・・・・・出
力回路、5・・・・・・出力端子、10・・・・・・基
板、11・・・・・・拡散層、12・・・・・・垂直レ
ジスタの転送電極、13・・・・・・転送ゲート電極、
14.14’ 、16・・・・・・不透明膜、7,8゜
9・・・・・・遮光された光電変換素子、40・−・・
・拡散層、42・・・・・・高濃度領域、晃2,53・
・・・・・垂直レジスタ領域、50.51・・・・・・
埋め込み層、54.55・・山・電界。
FIG. 1 is a conceptual structural plan view of an interline solid-state image sensor, FIG. 2 is a cross-sectional view taken along line AA', and FIG. 3 is a conceptual structural cross-sectional view showing an embodiment of the present invention. . 1...Photoelectric conversion element, 2...Vertical register, 3...Horizontal register, 4...Output circuit, 5...Output terminal , 10...substrate, 11...diffusion layer, 12...transfer electrode of vertical register, 13...transfer gate electrode,
14.14', 16... Opaque film, 7,8°9... Light-shielded photoelectric conversion element, 40...
・Diffusion layer, 42...High concentration region, Akira 2,53・
...Vertical register area, 50.51...
Buried layer, 54.55...mountain/electric field.

Claims (1)

【特許請求の範囲】[Claims] 一導電型を有する半導体基板上に形成された検数の光電
変換素子群と、複数列の埋め込みチャネル構造の垂直レ
ジスタ群と、該垂直レジスタ群の一端に隣接して設けら
れた水平レジスタと、咳水平レジスタの一端に設けられ
た出力回路と、前記光電変換素子群から前記垂直レジス
タへ周期的に信号電荷を移動せしめる手段と、眩光電変
換素子群の端部に位置する第一の当該光電変換素子群の
上部に設けられた遮光手段とを有するインターライン型
固体撮像素子において、前記第一の光電変換素子群と該
素子群に隣接して設けられた第一の前記垂直レジスタ群
との下部に形成された前記基板とは反対導電型の第一の
埋め込み層と、前記第一の光電変換素子群を含まない第
二の前記光電変換素子群と該第二の素子群に隣接して設
けられた第二の前記垂直レジスタ群との下部に形成され
た前記基板とは反対導電型の第二の埋め込み層とが互い
に分離して配置され、該第−と第二の埋め込み層との中
間領域の上部に遮光手段が設けられたことを特徴とする
固体撮像素子。
A plurality of photoelectric conversion element groups formed on a semiconductor substrate having one conductivity type, a vertical register group having a buried channel structure in multiple rows, and a horizontal register provided adjacent to one end of the vertical register group; an output circuit provided at one end of the horizontal register; a means for periodically transferring signal charges from the group of photoelectric conversion elements to the vertical register; and a first photoelectric converter located at an end of the group of photoelectric conversion elements. In an interline solid-state image sensor having a light shielding means provided above a conversion element group, the first photoelectric conversion element group and the first vertical register group provided adjacent to the element group a first buried layer formed at the bottom and having a conductivity type opposite to that of the substrate; a second group of photoelectric conversion elements that does not include the first group of photoelectric conversion elements; and a second group of photoelectric conversion elements that is adjacent to the second group of elements; A second buried layer having a conductivity type opposite to that of the substrate formed below the second vertical resistor group provided is disposed separately from each other, and the first and second buried layers are separated from each other. A solid-state image sensor characterized in that a light shielding means is provided above an intermediate region.
JP57008444A 1982-01-22 1982-01-22 Solid-state image pickup element Pending JPS58125971A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57008444A JPS58125971A (en) 1982-01-22 1982-01-22 Solid-state image pickup element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57008444A JPS58125971A (en) 1982-01-22 1982-01-22 Solid-state image pickup element

Publications (1)

Publication Number Publication Date
JPS58125971A true JPS58125971A (en) 1983-07-27

Family

ID=11693291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57008444A Pending JPS58125971A (en) 1982-01-22 1982-01-22 Solid-state image pickup element

Country Status (1)

Country Link
JP (1) JPS58125971A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100502620B1 (en) * 2000-02-17 2005-07-22 샤프 가부시키가이샤 Solid State Image Sensing Device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100502620B1 (en) * 2000-02-17 2005-07-22 샤프 가부시키가이샤 Solid State Image Sensing Device

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