JPS58123633U - Noise removal circuit - Google Patents
Noise removal circuitInfo
- Publication number
- JPS58123633U JPS58123633U JP1858682U JP1858682U JPS58123633U JP S58123633 U JPS58123633 U JP S58123633U JP 1858682 U JP1858682 U JP 1858682U JP 1858682 U JP1858682 U JP 1858682U JP S58123633 U JPS58123633 U JP S58123633U
- Authority
- JP
- Japan
- Prior art keywords
- output signal
- circuit
- signal
- monostable multivibrator
- noise removal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Noise Elimination (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図ａおよびｂは従来の雑音除去回路のブロック図。
第２図ａ、 ｂおよびＣは第１図ａおよび ｂに示した
従来の雑音除去回路の作用の説明に供する波形図。第３
図は本考案の一実施例のブロック図。第４図は本考案の
一実施例の作用の説明に供する波形図。第５図は本考案
の一実施例における単安定マルチバイブレータの具体的
−例を示す回路図。第６図および第７図は第５図に示し
た単安定マルチバイブレークの作用の説明に供する波形
図。
１・・・・・・信号ゲート回路、２・・・・・・増幅器
、３・・・・・・検波器、４・・・・・・自動利得制御
回路、５・・・・・・波形整形回路、６Ａおよび６Ｂ・
・・・・・単安定マルチバイブレータ、６５および６６
・・・・・・積分回路を構成する抵抗およびコンデン机
−第４図
第５図FIGS. 1a and 1b are block diagrams of conventional noise removal circuits. FIGS. 2a, b, and c are waveform diagrams for explaining the operation of the conventional noise removal circuit shown in FIGS. 1a and 1b. Third
The figure is a block diagram of one embodiment of the present invention. FIG. 4 is a waveform diagram for explaining the operation of an embodiment of the present invention. FIG. 5 is a circuit diagram showing a specific example of a monostable multivibrator in an embodiment of the present invention. 6 and 7 are waveform diagrams for explaining the action of the monostable multivib break shown in FIG. 5. 1...Signal gate circuit, 2...Amplifier, 3...Detector, 4...Automatic gain control circuit, 5...Waveform Shaping circuit, 6A and 6B・
...monostable multivibrator, 65 and 66
...Resistors and capacitors that make up the integration circuit - Figure 4 Figure 5
Claims (1)
回路への入力信号を増幅する増幅器と該増幅器の出力信
号を検波する検波器と該検波器の出力信号を入力して前
記増幅器の利得を制御する自動利得制御回路と前記検波
器の出力信号を波形整形する波形整形回路とを有し前記
自動利得制御回路の時定数を設定して雑音を検出する雑
音検出手段とを備えてなる雑音除去回路において、前記
波形成形回路の出力信号によりトリガされかつ出力信号
により前記信号ゲート回路を制御する第１の単安定マル
チバイブレータと、該第１の単安定マルチバイブレータ
により直接または積分回路を′ 介してトリガされかつ
前記第１の単安定マルチバイブレータの出力信号め開始
または終了時から所定設定時間、前記第１の単安定マル
チバイブレータの出力信号の発生を禁止する第２の単安
定マルチバイブレータとを備えてなることを特徴とする
雑音除去回路。A signal gate circuit inserted into a signal path, an amplifier that amplifies the input signal to the signal gate circuit, a detector that detects the output signal of the amplifier, and the output signal of the detector is input to determine the gain of the amplifier. Noise removal comprising: an automatic gain control circuit for controlling an output signal; a waveform shaping circuit for shaping an output signal of the detector; and noise detection means for detecting noise by setting a time constant of the automatic gain control circuit. a first monostable multivibrator triggered by the output signal of the waveform shaping circuit and controlling the signal gate circuit by the output signal; and a first monostable multivibrator directly or via an integrating circuit. a second monostable multivibrator that is triggered and prohibits generation of the output signal of the first monostable multivibrator for a predetermined set time from the start or end of the output signal of the first monostable multivibrator; A noise removal circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1858682U JPS58123633U (en) | 1982-02-15 | 1982-02-15 | Noise removal circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1858682U JPS58123633U (en) | 1982-02-15 | 1982-02-15 | Noise removal circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58123633U true JPS58123633U (en) | 1983-08-23 |
| JPS6246353Y2 JPS6246353Y2 (en) | 1987-12-14 |
Family
ID=30030838
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1858682U Granted JPS58123633U (en) | 1982-02-15 | 1982-02-15 | Noise removal circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58123633U (en) |
-
1982
- 1982-02-15 JP JP1858682U patent/JPS58123633U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6246353Y2 (en) | 1987-12-14 |
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