JPS58123151A - マルチプロセツサ・システムの動作方式 - Google Patents

マルチプロセツサ・システムの動作方式

Info

Publication number
JPS58123151A
JPS58123151A JP57187666A JP18766682A JPS58123151A JP S58123151 A JPS58123151 A JP S58123151A JP 57187666 A JP57187666 A JP 57187666A JP 18766682 A JP18766682 A JP 18766682A JP S58123151 A JPS58123151 A JP S58123151A
Authority
JP
Japan
Prior art keywords
cache
line
shared
private
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57187666A
Other languages
English (en)
Japanese (ja)
Other versions
JPS629942B2 (OSRAM
Inventor
ロバ−ト・パ−シイ・フレツチヤ−
デ−ビツド・モ−リス・スタイン
ア−ビング・ラドウスキ−・バ−ガ−
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS58123151A publication Critical patent/JPS58123151A/ja
Publication of JPS629942B2 publication Critical patent/JPS629942B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
  • Multi Processors (AREA)
JP57187666A 1981-12-31 1982-10-27 マルチプロセツサ・システムの動作方式 Granted JPS58123151A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/336,521 US4442487A (en) 1981-12-31 1981-12-31 Three level memory hierarchy using write and share flags
US336521 1981-12-31

Publications (2)

Publication Number Publication Date
JPS58123151A true JPS58123151A (ja) 1983-07-22
JPS629942B2 JPS629942B2 (OSRAM) 1987-03-03

Family

ID=23316475

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57187666A Granted JPS58123151A (ja) 1981-12-31 1982-10-27 マルチプロセツサ・システムの動作方式

Country Status (5)

Country Link
US (1) US4442487A (OSRAM)
EP (1) EP0083400B1 (OSRAM)
JP (1) JPS58123151A (OSRAM)
DE (1) DE3278948D1 (OSRAM)
ES (1) ES518678A0 (OSRAM)

Cited By (1)

* Cited by examiner, † Cited by third party
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JPH02294762A (ja) * 1989-04-12 1990-12-05 Internatl Business Mach Corp <Ibm> マルチプロセツサ・コンピユータ・システムおよびそのメモリ・アクセス方法

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DE3278948D1 (en) 1988-09-29
EP0083400A2 (en) 1983-07-13
US4442487A (en) 1984-04-10
JPS629942B2 (OSRAM) 1987-03-03
EP0083400B1 (en) 1988-08-24
ES8405533A1 (es) 1984-06-01
EP0083400A3 (en) 1986-06-04
ES518678A0 (es) 1984-06-01

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