JPS58123150A - Data processing system - Google Patents

Abstract

PURPOSE:To set or change automatically the state of a data processor, by reading the stored control information and then executing a process requested from the data processing side when the data processor delivers a maintenance instruction. CONSTITUTION:The address designated by the 2nd operand part is calculated by an operand address calculating circuit 11, and the OP code of an instruction set to a instruction register 10 is decoded by a decoder 20. When the OP code has the prescribed value, prescribed signal is transmitted to an interruption controlling circuit 21. Thus the circuit 21 turns on the prescribed interruption factor display bit of an interruption factor display register 22. An OR is secured for the contents of the register 22 through an interruption OR circuit 23 and then transmitted onto an interruption line 50. A scan-out control circuit 41 collects the scan-out data fed from each part of a data processor 100 and delivers them to a scan-out interface line 51.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a data processing system that includes a data processing device and a service processor that monitors, operates, and displays the system, when the data processing device issues a maintenance command. The present invention relates to a data processing system in which a processor reads control information stored in a storage device of the data processing device and executes processing requested by the data processing device.

Conventionally, when testing data processing equipment, a test program running on the data processing equipment is used to test the functionality of the data processing equipment. For this reason, in the past, operators had to use the control panel of the data processing equipment to set, control, and cancel various states. With this conventional method, it is not possible to save labor in testing;
In addition, since it requires manual intervention, it is not possible to avoid costs incurred due to operational errors. On the other hand, conventionally, the data processing unit #L has an instruction to issue an interrupt to the service processor and request all necessary processing on its behalf, but due to the recent increase in the scale and functionality of data processing units, the test program A large number of new commands (
Or, it was necessary to prepare an order (instruction). In order to support this large number of instructions, the hardware on the data processing device side and the processing agent log system on the service processor side will be enormous, which will reduce the amount of development man-hours and especially the memory and file resources of the service processor. It has become difficult to utilize it.

The present invention is based on the above considerations.

The purpose is to provide a data processing method that can automatically set and change the state of a data processing device without using a large amount of memory or files on the service processor side, and without full human intervention. It is said that Therefore, the data processing method of the present invention includes a first data processing device.

A first data processing device having a processor independent from the first data processing device and having a function of instructing the execution of control commands to be executed on the first data processing device, such as displaying and setting the internal state of the first data processing device. In a data processing system including two data processing devices, the first data processing device has an instruction for generating an interrupt in the second data processing device, and the first data processing device has an instruction to generate an interrupt to the second data processing device, and the first data processing device Control information for controlling the first data processing device is stored in a memory area within the processing device, and when a cough command is executed, the second data processing device uses the processor to transmit the control information. The present invention is characterized in that it decodes and sets control commands or data in control information on the first data processing device and executes them.

FIG. 1 is a diagram showing the configuration of one embodiment of the hardware interface of the present invention, the second factor is a diagram showing the program-module configuration of the service processor, and FIG. 3 is a diagram showing the configuration of the proxy instruction processing module. Figure 4 shows MNTA (
5 is a 70-chart showing the processing of the MNTA command, FIG. 6 is a diagram showing scan control information, and FIG. 7 is a diagram showing the structure of the scan control word (SCW). 8 is a diagram showing the configuration of the unit section, and FIG. 9 is a diagram showing the configuration of the data Φ address candy (D
AW), FIG. 10 is a diagram showing the configuration of the scan address word, FIG. 11 is a diagram showing the format of control information when r1=A, and FIG. ν is a diagram showing the configuration of the unit section. In Figure 1, 10 is an instruction register, 11 is an operand/address calculation circuit, and 11 is an operand/address calculation circuit.・Address register, add decoder, 21 interrupt control circuit, 22
is an interrupt cause indicator register, edict is an interrupt OR circuit, 30 is control information, chrysanthemum is a scan-in control circuit, 41 is a scan-out control circuit, catfish is a memory data conflict register, 5
0 is the interrupt line, 51 and 52 are the ink face lines, 100
1 denotes a data processing device, 101 a processor section, 102 a memory section, and 200 a service processor.

The data processing system includes a data processing device 100 and an in-service processor 200. service·
The processor 200 monitors, operates, and controls the system. The data processing device 100 includes a processor section 101 and a memory 5102. memory[
Control information 30 is stored in 102, and its first address is indicated by Ma. The processor section 101 includes an instruction register 10, an operand/address calculation circuit 11, one decoder for operand/address registers, an interrupt control circuit 21. Interrupt cause display register 22, interrupt OR circuit 2
3% scan-in system - circuit chrysanthemum, scan-out circuit 41
etc. The instruction word is set in the instruction register 10. In the case of the RX format as shown in the figure, the address power specified in the second operand section is calculated by the operand address calculation circuit 11. The OP code of the instruction set in the instruction register 10 is decoded by a decoder. When the OP code has a predetermined value, a predetermined signal is sent to the 1 interrupt control circuit 21. When a predetermined signal is input, the interrupt control circuit 21 turns on a predetermined interrupt cause display bit in the interrupt cause register n. The contents of the interrupt cause display register n are ORed by the interrupt OR circuit 23, and this OR signal is output onto the interrupt line. The scan-in control circuit 4o#'i sets the data sent from the service Φ processor 200 into latches, and applies all the various control signals to the registers.

The scan-out control circuit 41 is connected to the data processing device 110.
It collects scanout data sent from each part of the 0 and outputs it onto the scanout interface line 51. Service processor 200 is 1
Although not shown, it includes a processing device, memory, external storage device, display device, interface circuit, etc.
It can operate independently of the data processing device.

FIG. 3 shows the program module structure of the service processor 2000. Note that FIG. 2 only shows the relationship between proxy command processing, and the 5bSvP monitor activates a single-system device interrupt analysis module when an interrupt is issued from the data processing device 100. The main system device interrupt analysis module analyzes the cause of the interrupt and activates a processing module corresponding to the cause of the interrupt. When the interrupt is a diagnostic interrupt, the single-system interrupt analysis module activates all proxy instruction processing tasks.

FIG. 3 shows the configuration of the proxy instruction processing module. When the proxy instruction processing task is activated by the main system interrupt analysis module, the operating code analysis section of the proxy instruction processing task scans out the OP code in the instruction register 10 and detects the OP code corresponding to the OP code. Start the processing module. If the OP code is Xma88ma, the MNTA (maintenance) instruction processing module is activated.
1 FIG. 4 shows the structure of the program module of the MNTA instruction. The MNTA instruction glogram e module consists of an MNTA instruction individual processing part (main control part), a part that processes rl=O, and γ1=8
a part that performs the processing of yl=9, a part that performs all the processing of yl=9, and a part that processes r
It has a part that performs the processing of l=A. What is rl?MN
It shows the contents of the first operand part of the TA instruction. r1
When = 00, the central processing unit in the main system device is stopped, when rl = 8, scan-in processing is performed, when rl = 9, scan-out processing is performed, and γ
When 1=A, nine different processes are performed as specified by the control information.The processes performed when orl=A are unit e command processing, LD (load) pulse processing, and 5T.
ART pulse processing, 5TART CLOCK processing, A
SYNC (asynchronous) pulse processing, 0PSR set processing,
0P8R Recovery processing, etc. 0Note that the unit means an instruction unit, storage control unit, storage unit, channel unit, etc., and 0PSR means an operating status register.

5(a), (b), and (c) show the 70-chart of MATA instruction processing. Below, this 7a-chart will be explained.

■ When an interrupt is notified, the interrupt is accepted and the interrupt generating device is recognized.0 ■ A response routine corresponding to the interrupt source is activated. Note that the processes of ■ and ■ are executed by the SvP monitor.

■ The interrupt mask for the main unit is set and the cause of the interrupt is analyzed.

■ Check whether a diagnostic interrupt (DIAG RUPT) occurs. If it is Y-8, perform all the processing of ■ sN.

If not, perform other interrupt processing. Note that the processing of (1) and (2) is performed by the main system device interrupt analysis module.

■ Operation code (OP code) 0 determined by rascanout ■ Check whether the OP code is X'88' or not - check BL. If Yes, the %MNTA command will be issued.

Process (2) is performed, and if sNo is returned, other proxy command processing is performed. Note that the processes of ■ and ■ are executed by the operation analysis module.

■ Perform a rascan out of the first operand part (γ1 part) of the instruction register.

■ Check whether γ1 is "Om". If Yes, perform all the processing after C. s If No, perform all the processing of Find f〇〇 Transfer the area (control information area) whose starting address is the effective address to the memory of the service processor.

0 Connect all service processors and controlled units. The controlled unit receives control information (operation information).
It is determined from the UNIT or UNIT No data in the data).

0 Check whether γ1 is “8” or not. If the answer is Yes, 0 processing is performed, and if the answer is No, 0 processing is performed.

〇 Sends a scan-in pulse to the latch specified by the scan-in address in the operation data.

It is checked whether orl is 19''. If it is Yaa, process [phase], and if it is determined by sNo, process 31 after B is performed.

[Phase] Scanout in operating data
Scan out the latch specified by address.

[Phase] Store the scanout result in the memory address specified by the data address word (DAW).

Check whether Orl is A. If the result is ``Yes'', the [phase] process is performed, and if the result is ``No'', the abnormality process is performed.

[Phase] Extracts one operation seal data from the operation data set.

[Phase] Check whether it is the operation end. Yes
If s, process [phase], and if sNo, process [stock] □・1:.

The operation 1 that starts processing corresponding to each operation includes unit command processing, LD pulse processing, 5TART pulse processing, CLEAR pulse processing,
TART CLOCK pulse processing, ASYNCLOA
There are D pulse processing, 0PSR set processing, 0PSR recovery processing, etc.

[Phase] Next operation counter 1
Proceed to step 1 and process [phase].

■ Restore the connections between the service processor and each unit.

It is checked whether the OCPU is in the start mode or not. If it is 0Y11, it processes 0, and if it is sNo, it ends.

@ Performs CPU start processing 0 In addition, the CPU is not restarted during instruction step processing or address conveyor stop 0 γ1 = 8 processing (scan-in processing), rx = 9 processing (
The program that performs the following eight processes (scanout processing) and rl=A processing is a common control program that has already been created in order for an operator or the like to control the data processing device 10 (l) using the service processor 200.
The main control part of the NTA instruction processing tool is based on the operation information in the control information specified by the first operand section γ1 of the instruction register 10 and the operand address Ma.
The MNTA command is processed by starting and executing each of the existing programs according to the data.

Both the value of rl and the value of operand address Ma are obtained by scanout via interface lines 51 and 52.

As mentioned earlier, scan-in is performed when rl=8, and scan-out is performed when γ1=9. FIG. 6 shows the structure of scan control information. In FIG. 6, SCW is a scan control word, DAW
indicates a data address word, and SAW indicates a scan address word. The scan control word SCW is the seventh
The diagram shows the blind code 1”io p c
, unit specification section and scan bit length specification section S
It is composed of BC. Operation code part O
The 0 unit designation section UNIT, which is used by the PC to designate the scan-in method, has a configuration as shown in FIG. 8, and is used to designate the unit to be scanned in or scanned out. Scan bit length specification section S
BC indicates the bit length to be scanned in/out. The data address word DAW has a structure as shown in FIG. 9, and indicates an area (actual address) to be scanned out. Bits 30.31 are MO”
It is said that Scanout data is stored left justified in binary in the order specified. For missing bits in the last word, 'O' is stored. The scan address word SAW has the structure as shown in FIG. 1.theta.

The eleventh lid shows the format of control information when γ1=A. The unit number and data length are written in the first 4 bytes, the first 4 bytes are unused, and the operation data is written in the 8th and subsequent bytes.

The unit number is V, which has the configuration shown in Figure 12, and is the unit to be controlled. The specified 0 data length indicates the size of the operation Φ data section.69
, the maximum length is 2KB.

Figure 13 shows the operation data when all unit command processing is performed. Indicates operation 1 code, CMR is command register, ADRH is upper address register, ADRL is lower address register, DTRH is upper data register, DTR
L is the lower side of the data register, ENBR is the enable register.
Each register is shown. Each of the instruction unit, storage control unit, storage unit, and channel unit has a command register, an address register, and a data register. ENBR data is X'4000 for the instruction unit, X8000 for the storage unit, X1000 for the storage control unit, and X for the data channel.
By performing the master 2000 sector, the service processor 200 sends a command valid signal to each unit. The service processor 200 reads the above operation violation data, sets all specified data in each of the command register, address register, and data register in the specified unit, and turns on the command valid signal. shall be.

FIG. 13(b) shows operating data for performing the LD (load) pulse operation. The recommended operating code in this case is FIXX.

SAR indicates Select Address Register, ODR
indicates the output data register. Select address register 8 This is used to select the ARU register. When the service processor reads this operating data, it sets all the data in SAR and ODR and sends out a LOAD pulse. Then, even though the ODH data is loaded into the register selected by SAR, Figure 13 (c) shows the operation recommended data for performing 5TART pulse processing. , service processor 2
00 sets data in SAR and 1S T A RT
Send out a pulse. FIG. 13 e1 shows operating data for performing clear pulse processing. Reading this operating data will cause the service to
The processor sets all data in SAR, sends out CLEAR pulses, and performs 5TART CLOCK processing, AS
Operation code φ data for performing YNCLOAD pulse processing, 0PSR set processing, and 0PSR recovery processing is prepared.

As is clear from the above description, according to the present invention, it is possible to set a data processing device to various states without human intervention. It also has the advantage of requiring very few additional hardware and software resources.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of one embodiment of the hardware interface 721 of the present invention, FIG. 2 is a diagram showing the program-modiere configuration of the service processor, and FIG. 3 is the configuration of the proxy instruction processing module. Figure 4 shows MNTA (
5 is a flowchart showing the processing of the MNTA command, FIG. 6 is a diagram showing scan control information, and FIG. 7 is a diagram showing the structure of the scan control word (SOW). , Fig. 8 shows the structure of the unit section, and Fig. 9 shows the data address word (D
AW), FIG. 10 is a diagram showing the configuration of the scan address word, FIG. 11 is a diagram showing the format of control information, FIG. It shows the format of various operating recommendation data. DESCRIPTION OF SYMBOLS 10... Instruction register, 12... Operand address register, Adder... Decoder, 21... Interrupt control circuit, 22... Interrupt cause display register, 23...
・Interrupt OR circuit. Add...control information, 40...scan-in control circuit,
41...Scanout control circuit, 42...Memory data register, Group...Interrupt lines %51 and 52...
・Interface line, 100...Data processing device, 1
01... Processor section, 102... Memory section, 20
0...Processor in service. Patent applicant Fujitsu Limited (1 other person) Representative patent attorney
Kyo Tani Yobu Yu; Kuchi Matari 5 Shisha 1-l Shikashi 6 Figure Yaq Figure Sai 81 yen 1:. X9 figure 'Jto figure Y11 figure

Claims (1)

[Claims] A first data processing device and a processor independent of the data processing device, and execution of control commands executed on the first data processing device, such as displaying and setting the internal state of the first data processing device. In a data processing system comprising a second data processing device having an instruction function, the first
The data processing device has an instruction to generate one interrupt to the second data processing device, and the first data processing device stores the instruction in the memory area in the first data processing device specified by the operand part of the instruction. Store control information for controlling the
When executing the instruction, the second data processing device decodes the content of the control information, sets the control command or data in the control information on the first data processing device, and causes it to be executed. Data processing method.