JPS58127264A - Service processor - Google Patents

Abstract

PURPOSE:To operate an SVP.INTF from any side of two processors, by providing a processor interface circuit between two processors. CONSTITUTION:An SVP1 is directly connected to a CPU4 by a service processor interface 7, and also is connected to the CPU4 through an input/output control device (CH) 5 and a channel interface, by an I/O interface 8. The CPU4 and the CH5 are connected to a main storage device 6 by memory interfaces 10, 11, respectively. The SVP1 is constituted of two processors 2, 3, and the service processor interface 7 is connected to the processors 2 and 3 by one interface. Between the processors 2, 3, an inter-processor interface circuit is provided, and a command is outputted to the other processor optionally and its response is received, through the interface circuit under the control of a microprogram.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control method for a service processor composed of two processors.

In recent years, service processors (hereinafter abbreviated as SvP), which have both console and panel functions, have appeared in place of conventional computer panels. This SVP usually includes a keyboard (hereinafter abbreviated as KBD), a bar copy device (hereinafter abbreviated as HCOPY), a display device (hereinafter abbreviated as CRT), and a floppy disk (hereinafter abbreviated as CRT).
It is equipped with a service processor interface (abbreviated as SVP/INTF), which is connected to the CPU to monitor the internal operation of the CPU, and a data processor. I10 interface (hereinafter referred to as Ilo/INT) to operate as a console for inputting and outputting
(abbreviated as F).

This SVP consists of one processor, KBD, CR
When there is only one T etc., SVP, INTP, Ilo/IN
Controlling TF is not as difficult as it seems on the left. On the other hand, when the SVP consists of two processors and there are also two KDDs, CRTs, etc., it is extremely difficult to control the SVP/INTF, and conventionally, one of the processors was
, supports INTF, and the other supports console functionality and s
vp.

Only some service frames that do not use INTF were allowed. However, with this method, it is not possible to treat CRT%KBD etc. connected to two processors equally; for example, one CRT can only function as a console, which is unreasonable. there were.

The object of the present invention is to provide two processors, two CRTs, two
In an SVP consisting of two KBDs, etc., no matter which processor side's CRT or KBD is used, the SVP, INTF
The purpose is to make it easy to control.

A feature of the present invention is that a processor interface circuit is provided between two processors, and responses are exchanged between each microprogram that controls the two processors, so that the same processing can be performed from either side of the two processors. niS
It allows you to operate VP and INTF.

Hereinafter, the present invention will be described in detail according to an illustrated embodiment.

FIG. 1 shows an example of the configuration of a computer system with SvP to which the present invention is applied. 5vp1 is connected to a central processing unit (CPU) 4 by a service processor interface 7.
The input/output control device (CH) 5 and the channel interface 9 are directly connected to each other by the I10 interface 8.
It is connected to the CPU 4 via. The CPU 4 and CHs are each connected to the main memory 6 by a memory interface 10.11.
I'm connected to it. 5vP1 has two processors 2゜3
The service processor interface 7 is connected to the processors 2 and 3 through one interface. The present invention relates to a control system between processors 2 and 3 that constitute this 5VPI.

Details of the 5VPI shown in FIG. 1 are shown in FIG. 2. In FIG. 2, the processor 2 includes an arithmetic processing circuit 201%, a control storage (under JU, abbreviated as CB) 202, a keyboard adapter 203, and a keyboard (KB) connected to it.
D) 209, hard copy adapter 204 and hard copy device connected to it (H(13Y) 210.CP
U adapter 205, I10 interface adapter 20
6, a floppy disk adapter 207, and a floppy disk (F D ) 212 that is connected to the adapter 207 and can be shared with the processor 3. The configuration of the processor 3 is also exactly the same. processor 2
and 3 adapters 205 and 305 are commonly connected to the service processor interface 7, and similarly, adapters 206 and 306 are commonly connected to the 10 interface 8. 211 is an inter-processor interface circuit connecting processors 2 and 3, which is provided according to the present invention. That is, the present invention is capable of arbitrarily issuing commands to a partner processor and receiving responses thereof via the inter-processor interface circuit 211 under the control of microprograms stored in the CSs 202 and 302. This allows equivalent operations to be performed from two processors 2 and 3.

FIG. 3 shows an example of a microprogram group stored in the CS 202, 302, and the relationship between an interrupt factor group for activating the microprogram group and its interrupt level. In FIG. 3, 401 is a group of microprograms, of which a microprogram for interrupt level 2 inter-processor response and a level 7
The following task microprograms are related to the present invention. 40
2 is an interrupt priority circuit that determines the priority order of the interrupt request group 403, and is actually the arithmetic processing circuit 20 in FIG.
1, part of 301. The interrupt factor group 403 includes:
Reset instructions and debugging interrupts from the panel, processing requests for other processor errors, processing requests for own processor errors, processing requests for power CTL errors, processing requests from other processors, input processing requests from the keyboard, requests from the CPU There are processing requests, processing completion interrupts from the CPU, etc.

FIG. 4 shows a detailed diagram of the inter-processor interface circuit 211 and the relationship between the interface circuit and the microprograms at interrupt levels 2 and 7 in the processor 2.3. In FIG. 4, 404 and 407 are level 2 inter-processor response microprograms, 405 and 40
8 indicates a level 7 task microprogram. 40
6, 409 are microprograms 404, 405
, or control flags set and reset by 407 and 408. Also, 410, 41
1 is an information holding circuit such as a register. The operations in FIG. 4 are as follows: (1) Control for notifying the second processor 3 of the change in state that has occurred on the first processor 2 side; (2) The state that has occurred on the second processor 39111; Behind the change, ′? 4JJl's processor 2111II. In this case, the microprogram of the first processor 2 takes the initiative and drives the inter-processor interface circuit 211 at a predetermined cycle, and the microprogram level 2 of the second processor 3
In response, the second processor 3 drives the inter-processor interface circuit 211 and interrupts the first processor 3.
Assume that a method is adopted in which an interrupt is issued to the microprogram level 2 of the processor 2.

Below, we will take the case where the operator instructs IPL (initial program load) as an example, and the above +11,
+21 control will be described. IPL means starting the operating system (O8), and includes initializing resources managed and used by the operating system. SvP includes, for example, initializing a hardware mask and initializing CPU-related control flags managed by a microprogram.

First, when IPL is instructed on the first processor 2 side,
The first processor 2 needs to notify the second processor 3 that an IPL operation has been instructed. FIG. 5 shows the flow of microprogram level 2 and task level (level 7) programs of the microprograms built into the first processor 2, and the flow of the microprograms built into the second processor 3. It shows the flow of the microprogram level 2 and task level programs and the operation of the interprocessor interface circuit 211.

This will be explained below based on FIG.

Among the microprogram group 405 at microprogram level 7 of the first processor 2, the microprogram related to IPL is sent to the central processing unit (CPU) 4 via the service processor interface 7 in step F1.
Start IPL to.

After that, after receiving the TPL end signal via the service processor interface 7 (step F2)
, initializes the I-doware mask of the first processor 2, and initializes CPU-related control flags (step F3). Then step 4
The microprogram sets information to the information set line 414 indicating that IPL has been instructed by the first processor 2,
The inter-processor interface circuit 211 is notified. The inter-processor interface circuit 211 transfers the contents of the information set line 411 to the information holding circuit (COM REG) 4
At the same time as setting the flag to 10, the interrupt line 417 is driven, and an interrupt is generated to drive the microprogram group 407 of the microprogram level 2 of the second processor 3.

In the microprogram group 407 of the microprogram level 2 of the second processor 3, in step G1, the first processor 2 of the inter-processor interface circuit 211
reads the information instructed by through the information output line 416. Next, by analyzing this information in step G2, it is known that IPL has been instructed in the first processor 2. Therefore, in step G3, the hardware mask and CPU-related control variables in the second processor 3 are initialized. Thereafter, in step G4, the information set line 418 is put on the information set line 418 to notify the inter-processor interface circuit 211 that the operation related to IPL in the second processor 3 has been completed.

The inter-processor interface circuit 211 transfers the contents of the information set line 418 to the information holding circuit (COMBEG) 4.
11, the interrupt line 413 is simultaneously driven to generate an interrupt to start the microprogram group 404 of the microprogram level 2 of the first processor 20.

The microprogram group 404 of the microprogram level 2 of the first processor 20 reads the information instructed by the second processor 3 of the interprocessor interface circuit 211 via the information line 415 in step 111. And then the next step. By analyzing this information in step H2, it is known that it is a termination response. In step H3, a predetermined control flag 406 in the control storage 202 is set. On the other hand, the microprogram at microprogram level 7 that first interrupts the second processor 3 is looping for this control flag 406 to be set in step F5, so the IPL is completed at this point. As such, proceed to the next operation.

Note that while the microprogram of microprogram level 2 is being executed, the execution of the microprogram of microprogram level 7 is suppressed, so this is indicated by a broken line in FIG. 5 as task stealing.

Next, control when IPL is instructed on the second processor 3 side will be described. FIG. 6 shows the operation of the microprogram and RAM at this time using a flow similar to that of FIG. The following will explain based on FIG. 6.

The microprogram related to IPL in the microprogram group 408 of the second processor 30 microprogram level 7 is sent to the central processing unit (CPU) via the service processor interface 7 in step J11.
)4 to start IPL.

Thereafter, after receiving the IPL end signal via the service processor interface 7 (step J1
2) Initialize the hardware mask of the second processor 3, initialize CPU-related control flags, and set a predetermined control flag 409 in the control storage 302 to the effect that an IPL instruction has been issued (step J13). . In this state, the microprogram related to IPL of the second processor 3 loops (step J14).

On the other hand, as mentioned above, since the first processor 4)-2 has the initiative, some request is made within the second processor 3 among the microprogram group 405 of microprogram level 70 within the first processor 2. In a microprogram that determines whether the
Set the makeshift information on the information set line 414 with il,
The inter-processor interface circuit 211 is driven. The inter-processor interface circuit 211 connects the information set line 4
14 into the information holding circuit 410, and at the same time drives the interrupt line 417 to generate an interrupt to start the microprogram group 407 of the second processor 30 microprogram level 2. The operation of the inter-processor interface circuit 211 at this time is the same as the operation when the inter-processor interface circuit 211 is driven in step F4 of FIG.

In the second processor 30 microprogram level 20 microprogram group 407, in step G11, the first processor 2 of the inter-processor interface circuit 211
reads out the information instructed by through the information readout line 416. As a result, when the microprogram related to IPL of the second processor 3 enters a loop at step J14 and the first inquiry is received from the first processor 2,
The inquiry is learned in the next step G12. Step G
In step G13, it is learned that IPL is instructed in a predetermined control flag 409 in the control storage 302, and in step G14, the second processor p3-(
1" IPL is indicated on the information set line 418. If there is no change, information of no change is placed on the information set line 418 in step G15, but in this example, this case will be explained. is omitted.

By driving the information set line 418, the inter-processor interface circuit 211 connects the information set line 41
At the same time, the contents of 8 are set in the information holding circuit 411, and the interrupt line 413 is driven to generate an interrupt to start the first processor 20 microprogram level 20 microprogram group 404. The operation of the inter-processor interface circuit 211 at this time is the same as the operation when the inter-processor interface circuit 211 is driven in step G4 of FIG.

The microprogram group 404 of the microprogram level 2 of the first processor 2 reads the information instructed by the second processor of the interprocessor interface circuit 211 via the information line 415 in step H1l. In step H13, the first processor 2 knows that it is a temporary response to the second processor 3, and sets the predetermined control flag 406 in the control storage 202.
Set.

Then, in step H13, a response is returned to the second processor 3.

In step G16 of the microprogram level 2 of the second processor 3, in response to the response from the first processor 2, a predetermined flag 409 in the control storage 302 is reset, and the microprogram level 2 is exited. At this time, microprogram level 7
The program is restarted (step J14 resumes execution), and the flag 409 is reset.
The microprogram related to PL is completed and the process proceeds to the next operation.

On the other hand, on the first processor 2 side, after exiting microprogram level 2, the program in step F12 is restarted, step 13 is executed, and at this time, the second processor 3 knows that IPL has been instructed. . Therefore,
In step F14, the first processor 20's hardware mask is made normal, CPU-related control flags are initialized, and the process proceeds to the next step.

The above has been explained using IPL as an example, but even if, for example, the first processor 2 wants to make the task of asking the second processor 3 whether there is a request or not based on a predetermined cycle, It is clear that the present invention is applicable. That is, it can be seen that by applying the present invention, the first processor 2 and the second processor 3 can be controlled synchronously as if they were the same processor.

Further, in this case, it is assumed that the first processor 2 has the initiative, but it is clear from the above description that it is within the scope of the present invention even if the second processor 3 has the initiative.

As is clear from the above description, according to the present invention (2), an SVP consisting of two processors facilitates mutual control of the processor f[, and allows the two processors to have equivalent functions.

[Brief explanation of the drawing]

Figure 1 is an overall configuration diagram of a computer system having a service processor to which the present invention is applied, Figure 2 is a detailed diagram of the service processor in Figure 1, and Figure 3 is a microprogram stored in the control storage of the service processor. FIG. 4 is a diagram showing the relationship between the microprogram group in the processor and the inter-processor interface circuit, and FIGS. 5 and 6 are diagrams showing the schematic operations of FIGS. 2 and 4. It is. 1... Service processor (SVP), 2.3...
Processor, 4... Central processing unit (CPU), 5
... input/output control device, 6... main storage device, 7...
Service processor interface, 8... I10 interface, 9... Channel interface, 10
．． 11...Memory interface, 201, 301
. . . Arithmetic processing circuit, 202, 302 . . . Control storage, 211 . . . Inter-processor interface circuit. Figure 1 Figure 2

Claims (1)

[Claims] 1. Has multiple microprogram running levels,
If a more urgent condition occurs while a microprogram is running at a lower level, the processing of the currently running microprogram is temporarily interrupted, a higher level microprogram that meets the emergency condition is executed, and then the process is temporarily interrupted. In a service processor configured with two microprogram-controlled processors that allow microprogram processing to continue, the two processors are connected by an interprocessor-interface circuit, and one processor is connected to the The interface circuit is driven to interrupt the microprograms of the other processor, and in response, the other processor drives the inter-processor interface circuit to interrupt the microprograms of the 10,000 processors, thereby interrupting the two processors. A service processor characterized by having equivalent functions.