JPS58129568A - Computer system with auxiliary service computor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a computer system, and more particularly to a main computer that processes digital information and an auxiliary service computer that frees the main computer from some auxiliary functions to improve system operation. It is related to a computer system including.

Besides executing the main program, a digital processing device performs many auxiliary functions, such as data transfer with peripheral devices (i.e. terminals, printers).

The master central processing unit (-) performs initial go/no-go tests or periodic self-test operations, execution of terminal interface program commands from user terminals and maintenance terminals, etc. Jiekuze responds to this by extracting the interrupt vector and executing the current program.
The time spent storing status and servicing the CPU interrupts varies from tens of microseconds to hundreds of microseconds, excluding the time required by the actual service routine.

This is because it is necessary to interrupt program execution and execute routines for translating and formatting input and output data. In this way, it is desirable to eliminate the time spent servicing interrupts.

Traditional processing devices require hardware (i.e., watched: yatchdog) to test themselves.
motor, wrap-around
) links etc.) and use ζ de υ software. Main elements of processing equipment testing (-1 bus.

(memory, software) cannot test themselves, so it is difficult to obtain a wide test coverage. The watchdog monitor can detect a limited percentage of faults (approximately 6J").' To obtain a wide test coverage, it is essential to be able to thoroughly test key elements.

In maintenance or debug mode, the software includes a universal asynchronous receiver/transmitter (UART) required for serial input/output, counters required by the UART and the watchdog monitor, etc.

To date, programs have been stored in read-only memory (FROM).
), the initial software development was a problem for the built-in computer system. When you have finished correcting the bug, you can either write and load the program into a set of FROMs, or use a means such as an auxiliary RAM board to install the software.
Configured to connect to the software development stage set,
Download the corrected software (down 1)
oad) l, had to.

Accordingly, seven objects of the present invention are to provide an improved system that has a high range of testing capabilities, including testing of the main requirements, and that allows the operator to interact with the main computer with minimal interruption to the real-time operation of the main computer. The objective is to provide a computer system with improved performance.

Another object of the present invention is to
It is an object of the present invention to provide a computer system capable of performing a variety of functions and minimizing the hardware required to interpret commands generated from a terminal.

Yet another object of the present invention is to provide a computer system that can minimize interrupt periods when accessing peripheral devices.

Yet another object of the present invention is to provide a computer system in which portions of the operating system that perform self-test, watchdog monitor, and user interface functions are localized within a service computer.

Yet another object of the present invention is to provide the system with download capabilities for the purpose of developing programs.

Other objects and advantages of the invention will become apparent from the description below.

A computer system according to the present invention includes a main computer for processing digital information and a local bus for interconnection. The service computer is connected to the main computer via a local bus and provides testing capabilities for the system's hardware and software, while minimizing operator interaction with the main computer and interrupting the real-time operation table of the main computer. improve system operation by making it possible to

Contains two real-time counters, a general purpose asynchronous receiver/transmitter.

Referring to the drawings, FIGS. 1A and 1B illustrate a preferred embodiment of a computer system according to the present invention. A main computer 10 is provided for processing digital information. The main CFυ computer 10 is a central processing unit (he-seven) 11. Program and data memory12. System bus interface 13. Clock 14. Input/output equipment, receiver/transmitter 15. User terminal 16. and fast/slow FROM
It includes a switch 17. Also included is an interconnect bus 20 and a service microcomputer or processing unit 30 connected to the main computer 10 via the bus 20, which provides system hardware and software testing capabilities as well as operator main To improve system operation by enabling interaction with a computer to such an extent that interruption to the real-time operation of a main computer is not a problem. In the example, a single chip zilog Z(+') microcomputer with serial input/output ports is chosen as the service microcomputer.

ROM, j? Includes a bit counter, universal asynchronous receiver/transmitter (UART).

As shown in the figure, a master/slave protocol (pr
control of the busbar is performed by Slave or service computer 30 grants access to the bus by activating bus request line 41.

In the serial input/output mode, the UAR of the microcomputer
T performs the conversion from serial format to parallel format, and microcomputer 30 stores the data and makes processing decisions as to what to do with the data. Data is transferred to the master RAM only when needed, and in blocks when applicable.

In normal input operation, the UART interrupts the service microcomputer 30 and the service microcomputer stores the data in its RAM. At the end of the message, the service microcomputer interprets the command and generates a bus request signal for the command (ZJ002).

Upon receiving the busbar confirmation signal, the Service 6 microcomputer is interrupted for only a few microseconds, as opposed to the hundreds of microseconds in the case of conventional interrupts, when it receives a formatted boot message. be.

Data can also be transmitted according to commands from the data center e@311. In normal output operation, the Z/θ/processor 11 places its output data into a buffer area in local memory. Next is Zt! ”00/The processing unit instructs the z(5> service microcomputer 30 by writing an instruction to the ZJ' boat of the data mother 1131. This interrupts the microcomputer and causes the microcomputer to format the data in a predetermined format. Run the appropriate routine and then
Send data via.

The service microcomputer 30 is the main computer 10
with full testing capabilities. i.e. initial (foreground) mode or periodic (background)
mode, as well as easy or high range pass/fail (go/no
-go) Inspection. However, because its program memory is small (,2/Fk), the service microcomputer 30 has a high range of main l! ! Limited to elemental tests. That is, executing a test routine and having the service microcomputer 30 compare the result with a predetermined value or with a result calculated in parallel by the main processor. To initiate these tests, service microcomputer 30 interrupts main computer 10 and directs it to the test routine via an interrupt vector. If the test result is positive,
The main computer continues its operation. If the test result is negative,
The main computer is stopped and a fault is displayed.

Since the service microcomputer 30 has its own clock, it not only acts as a watchdog monitor, but also acts as an intelligent (1ntel)
l igent ) also acts as a watchdog monitor. Service microcomputer 30 starts a counter at the beginning of the master repeat period and also interrupts main processor 11 to request an immediate response. The service microcomputer 30 will indicate a fault if its timer overflows before receiving the response or confirmation signal. The period of the watchdog monitor can be easily changed by loading different limit values into the counter.

As will be apparent to those skilled in the art, the computer system of the present invention has significant advantages. When used as an intelligent serial input/output device, the service microcomputer 30 replaces the UART and counter/timer chips.

When used as an intelligent direct memory access device, the time the main computer 10 is away from the main program is reduced by at least seven orders of magnitude (tens of microseconds becomes a few microseconds).

When acting as a system monitor, the service microcomputer 30 receives a number of system commands of the main computer, such as "stop,""continue," and "reset," as well as "displays" that are transmitted serially from the terminal 16 to the service computer. ”, “Enter”, “Execute”, “Single Step”,
It can recognize and execute common debugging commands such as "test,""register," and "power up."
When operating as a tester, the service microcomputer 30 can test the master computer over a wide range of applications, including the main components.

Also, watchdog monitoring functions can be performed without extra hardware. Series input/output, testing,
In addition to monitoring functions, service computers can perform many additional functions with little or no additional hardware.
.

It is at the point where it wilts. In a typical application, data words in local memory are read periodically by main processor 11. Access to local memory uses a bus request and bus acknowledge process and does not interrupt the main processing unit. In fact, the speed reduction is slight, on the order of 70 microseconds per byte. Furthermore, this monitoring action is intelligent. This is because the service processor can analyze the retrieved memory snapshot and make an initial selection (5clean).

During the software development stage of the system, high-speed/low-speed FR
The OM switch 17 is used to prohibit the main computer from attempting to execute the program.

Instead, control is maintained by service computer 30.

Although a computer system according to a preferred embodiment of the invention has been described, it will be apparent to those skilled in the art that various changes and modifications can be made to the configuration and means used without departing from the true spirit and scope of the invention. That's probably the case. For example, both the main computer and the service computer can be configured with a single VLSI chip.

Furthermore, complexity can be reduced by using a small microcomputer as a service computer.

[Brief explanation of the drawing]

FIGS. 1A and 1B are block diagrams showing preferred embodiments of the computer system of the present invention. Explanation of symbols 10...Main computer, 11φ...1ze, 12...Program data memory, 130-System bus interface, 14...Clock, 15...Receiver/transmitter, 16 ...User terminal, 20...Interconnection bus, 30-...Service φ microcomputer, 41-0
Bus line request line, 42... Bus line confirmation signal. Drawing 7'('s!F (no change in content) voluntary method of writing procedural amendments) 1. Case Description 1982 Patent Review No. 223097 2 Title of the Invention Computer System with an Auxiliary Service Computer 3 Person Making Amendment Relationship to the Case Applicant Address River Road, Schenectaday, New York, 12305, United States of America 1 Name: General Electric Company Representative: Arthur M. King 4, Agent address: 4th floor, Kowa Pill, 35, 1-14-14 Akasaka, Minato-ku, Tokyo 107, Japan General Electric Co., Ltd., Far East Patent Department 5. Subject of amendment 6. Contents of amendment (1) The name of the representative in the patent applicant column of the application is corrected as shown in the attached sheet (application for correction). (2) Engraving of drawings (no changes in content) (3) Submission of power of attorney 7, list of attached documents

Claims (1)

[Scope of Claims] / A main computer for processing digital information, an interconnection bus, connected to the main computer via the interconnection bus, and equipped with the ability to test system hardware and software; and a service computer that improves system operation by allowing interaction with the main computer with less interruption to the real-time operation of the main computer. 2. The computer system according to claim 1, wherein the service computer includes a microcomputer and a universal asynchronous receiver/transmitter (UART). 3. A computer system according to claim 2, in which a counter and a UART are serially connected to form a watchdog-monitor and a repeat counter. In the computer system according to claim 1, bus control is performed between the main computer and the service computer by a main/service protocol that exclusively accesses one or the other bus. computer system. In the computer system according to claim 1, the service computer requests access to the bus by activating the bus request line, and the main computer grants access by means of a bus confirmation signal. 6. The computer system according to claim 1, wherein the service computer performs a serial input/output port function. 7. The computer system according to claim 1, which includes a user terminal, and a service computer performs an interface function between the main computer and the user terminal. ! The computer system according to claim 1, wherein the service computer performs a timing function and a control function for performing a self-test of the system. 9. A computer system according to claim 1, in which the two-service computer performs a real-time monitoring function of data contained in the main computer.