JPS58121451A - Error detection controlling system of microprogram processing device - Google Patents

Abstract

PURPOSE:To minimize the loss in time and improve the usability of a control storage, by continuously inspecting the validity of output data in the data reading out cycle and, when a correct data is obtained, by using the said data. CONSTITUTION:When an error exists in data outputted from a control storage 1 and an error detect signal is generated from an error detecting circuit 5, a data reading out gate 7 is kept under a closed condition and no data taking-in to a data register 2 is performed. In this case, the error detection is informed to an address updating timing implementing circuit 6 by an error detect signal line 9 and a delay of the address updating timing is assigned, and the timing is delayed until the timing of the next clock. In this way, the updating to a control storage address register 4 is delayed and an operating circuit 3 is also set to the waiting condition.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an error detection control method in a microprogram processing device, and in particular to a convex technology related to an error detection control method that increases the availability of control memory. Background In microprogram processing devices that proceed with processing by issuing microinstructions one after another from a control memory that stores microinstructions, if there is an error in the data (microinstructions) issued from the control memory, it can lead to hardware malfunction. Therefore, the use of the read data must be prohibited.O Pl Prior Art and Problems In the past, when a read data busy error from the control memory is detected, the system immediately stops the operation and reports the error. However, the former method reduces the availability of control memory, while the latter method improves availability but takes twice as long to read. Ta.

B) Purpose of the Invention The present invention continuously checks the validity of output data in cycling data read from control memory, and uses the data when correct data is obtained. The purpose is to reduce time consuming as much as possible and increase the availability of control memory.

(E) Structure of the Invention In order to achieve the above object, the present invention comprises a control memory for storing microinstructions, a control memory address register, a data register for holding microinstructions read from the control memory, and a skeleton data register. In the second error detection control method in a microprogram processing device having an arithmetic circuit that performs arithmetic processing according to the contents of a register, when read data from the control memory is checked and an error is detected in the read data, the K is set so that the read data is not set in the data register, and updating of the control storage address register is delayed, and thereafter, checking of the read data from the control storage is continued for a preset period.

When the error in the read data disappears within the period,
The correct read data is set in the data register, and the control storage address register is updated with a delay from the normal time by the cough data set delay time.

Not limited to control memory, but in general memory elements, even if data cannot be read correctly due to an increase in delay time due to deterioration of element characteristics due to aging, etc., increasing the read time will increase the delay time. There is a possibility that the data can be read correctly by absorbing the delayed delay time. Taking this into consideration, the present invention extends the start-up time to the minimum necessary length so that the output data of the control memory can be read correctly. Embodiment of the Invention FIG. 1 is a block diagram of a main part of a microprogram processing device according to an embodiment of the present invention. In FIG. 1, L indicates a control memory;
8 is a data register, 8 is an arithmetic circuit 1, 4 is a control storage address register, 5 is an error detection circuit, 6 is an address update timing generation circuit, 7 is a data read gate, 8 and 9
is an error detection signal 11, 10 is an address update timing signal line, and 11 is a read data line.

FIG. 2 is a time chart of the embodiment.

Hereinafter, the operation of the embodiment will be explained with reference to the time chart in FIG. 2. Normally, the data reading period from the control memory I is t,
Data is the output data signal from the control memory l.

The timing for inputting data into the register 3 is determined as shown in the figure. In other words, the output data signal is set in the data register 2 by a clock at one point.

On the other hand, if there is an error in the output data from the control memory 1 and an error detection signal is issued from the error detection circuit 5 at one point in the illustrated timing.

The data read gate 7 is closed and data is not read into the data register 2. At this time, the error detection signal 119 notifies the address update timing generation circuit 6 of the error detection, and the address update timing generation circuit 6 is notified of the error detection signal 119. Typing delay is indicated. Then, wait until the timing 6 shown in the figure when the next clock appears. As a result, the update of the control storage address register number is delayed by 12 hours as shown in the figure, and the arithmetic circuit 8 is also forced to wait for the time t'. Second
The example in the figure shows a case where the data is read normally after 12 hours, which is l clock period, or if an error continues to occur at point B, wait an additional 17 hours. I am made to look at it. In this embodiment, control memory readout Kl! The time to do it is heron+nt'
Ofl, which is (n=Oelet.--.=), changes depending on the element delay time of the control memory, and when it exceeds a certain predetermined value, time extension is stopped and an error report is performed.

(Effects of the invention) According to the invention, an increase in delay time due to deterioration of the characteristics of control memory elements can be relieved with the minimum necessary time loss, without significantly impairing the performance of the microprogram processing device. It has the advantage of increasing the availability of control memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of main parts of a microprogram processing device according to an embodiment of the present invention, and FIG. 2 is a time chart of the embodiment. In the first rIA, l is a control memory, 2 is a data register, 8 is a -g path, ii is a control memory address register, b is an error detection circuit, and 6 is an address update timing generation circuit.

Claims (1)

[Claims] A microprogram that has a control memory that stores microinstructions, a control memory address register (7), a data register that is read from the control memory and holds nine microinstructions, and an arithmetic circuit that executes arithmetic processing according to the contents of the data register. In the error detection control method in the processing device, the read data from the control memory is checked.
*When an error i is detected in the read data, the command prevents the read data from being set in the data register, delays the update of the control memory address register, and then updates the control memory for a predetermined period. When the read data error disappears within the period, the correct read data is set in the data register, and the read data is delayed by the data set delay time from the normal time. The microphone is characterized in that it updates the control storage address register.