JPS58117726A - Signal switching circuit - Google Patents
Signal switching circuitInfo
- Publication number
- JPS58117726A JPS58117726A JP78582A JP78582A JPS58117726A JP S58117726 A JPS58117726 A JP S58117726A JP 78582 A JP78582 A JP 78582A JP 78582 A JP78582 A JP 78582A JP S58117726 A JPS58117726 A JP S58117726A
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- signals
- period
- switching
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
- H03K17/62—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors
Abstract
Description
【発明の詳細な説明】
本発明は、4つの回路系からの信号を順次切換えて取出
し、合成した波形を作り出す場合に使用できる信号切換
回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal switching circuit that can be used to sequentially switch and extract signals from four circuit systems to create a combined waveform.
上記のように4つの回路系からの信号を順次切換えて取
出し、合成した波形を作り出す場合、一般的には第1図
に示されるような構成にて切換パルスを90度ずつ異な
らせて信号を順次切換える方法が採用されていた。以下
、この従来例について簡単に説明しておく。To create a composite waveform by sequentially switching and extracting signals from four circuit systems as described above, generally the switching pulses are changed by 90 degrees to generate the signals using the configuration shown in Figure 1. A method of sequential switching was adopted. This conventional example will be briefly explained below.
先ず第1図において、4つの異なった信号が入力端子1
,2,3,4に加えられ、切換器9にて第2図に示すパ
ルスa、b、c、dにより切換えられることになる。そ
のためには、4つの切換パルスa〜dをパルス周期の1
/4のパルス幅を持つパルスとし、かつ位相を90度ず
つ異ならせて互いに重なり合わないようにして切換器9
に与えなければならない。このようなパルスを作り出す
ことは回路として複雑となり容易であるとはいえない。First, in Figure 1, four different signals are input to input terminal 1.
, 2, 3, and 4, and are switched by the switch 9 using pulses a, b, c, and d shown in FIG. To do this, four switching pulses a to d must be set at 1 pulse period.
The switching device 9 uses pulses with a pulse width of /4 and makes the phases different by 90 degrees so that they do not overlap with each other.
must be given to Creating such a pulse requires a complex circuit and cannot be said to be easy.
本発明は上記問題を除去するもので、信号を切換えるパ
ルスとしてパルスの周期の1/2のパルス巾を持つパル
スでもって、4種類の信号を順次切換え得るものである
。以下、本発明の一実施例について第3図〜第5図を用
いて説明する。The present invention eliminates the above problem and allows four types of signals to be sequentially switched using a pulse having a pulse width of 1/2 of the period of the pulse as a pulse for switching the signal. An embodiment of the present invention will be described below with reference to FIGS. 3 to 5.
第3図の入力端子1.2,3.4にそれぞれ第4図e
r f r g + hのごとき4種類の信号が与えら
れ、端子11には第4図のiのようなデユーティ6o%
の切換パルスが加えられるとする。端子1.2,3.4
に与えられた入力信号は、入力信号e、fは切換器12
において、入力信号g、hは切換器13において、おの
おのパルスiによって切換えられる。例えば、切換器1
2において、切換パルスiが“H”の期間では端子1か
らの入力信号eが出力され、!1 L”の期間では端子
2からの入力信号fが出力される。すなわち、切換器1
2の出力としては第4図のjあようになる。同様に、切
換器13において、切換パルスiが“H”の期間では端
子4からの入力信号りが出力され、”L”の期間では端
子3からの入力信号gが出力される。従って、切換器1
3の出力は第4図のkのようになる。4 e to the input terminals 1.2 and 3.4 in FIG. 3, respectively.
Four types of signals such as r f r g + h are given to the terminal 11, and the duty is 6o% as shown in Fig. 4.
Assume that a switching pulse of is applied. Terminals 1.2, 3.4
The input signals e and f are input to the switch 12.
Input signals g and h are switched in a switch 13 by each pulse i. For example, switch 1
2, during the period when the switching pulse i is "H", the input signal e from the terminal 1 is output, and ! 1L” period, the input signal f from the terminal 2 is output. That is, the input signal f from the terminal 2 is output.
The output of 2 will be as shown in jA in Figure 4. Similarly, in the switching device 13, when the switching pulse i is "H", the input signal from the terminal 4 is outputted, and when the switching pulse i is "L", the input signal g from the terminal 3 is outputted. Therefore, switch 1
The output of 3 is as shown in k in Fig. 4.
さらに、切換器12,13の出力を切換器15に加える
。ここで切換器15にて波形j、kを切換えるパルスと
しては、端子11に与えられたパルスiを移相器14に
て位相を9o度ずらしたものとする。このパルスを第4
図の1に示す。このパルス1がH”の期間では切換器1
5の出力は切換器12の出力jとなり、“L″′の期間
では切換器13の出力にとなる。従って、切換器15の
出力としては、切換器12.13の出力が交互に切換わ
ることとなり、結果的には入力信号e、f。Furthermore, the outputs of the switches 12 and 13 are applied to the switch 15. Here, the pulse for switching the waveforms j and k by the switch 15 is the pulse i applied to the terminal 11 whose phase is shifted by 90 degrees by the phase shifter 14. This pulse
Shown in Figure 1. During this period when pulse 1 is “H”, switch 1
The output of 5 becomes the output j of the switch 12, and becomes the output of the switch 13 during the "L"' period. Therefore, as the output of the switch 15, the outputs of the switches 12 and 13 are alternately switched, resulting in the input signals e and f.
g、hを順次切換えた出力(第4図のm)が得られるこ
ととなる。An output (m in FIG. 4) obtained by sequentially switching g and h is obtained.
第3図の具体回路例を第5図に示す。第3図と同様に入
力端子1,2,3.4に4種類の信号を印加し、端子1
1にデユーティ50%の切換パルスを与えた場合を考え
る。この切換パルスのレベルが抵抗37.38の分割比
で決まる電圧より高い場合はトランジスタ17.19が
ON状態、トランジスタ16,20がOFF状態となり
、入力端子1に印加した信号がトランジスタ30のベー
スに加わる。これと同時にトランジスタ23.25もO
N状態となり入力端子4に印加した信号がトランジスタ
330ベースに加わる。一方、切換パルスのレベルが抵
抗37.38の分割比で決まる電圧より低い場合は逆に
トランジスタ16 、20゜22.27がON状態、ト
ランジスタ17,19゜23.25がOFF’状態とな
り、入力端子2,3に印加した信号がトランジスタ30
.33のベースにそれぞれ加わる。従って、トランジス
タ30のベースには入力端子1,2に印加された信号が
、トランジスタ33のベースには入力端子4,3に印加
された信号が、おのおの端子11に与えられた切換パル
スによって交互に加わる。ただし、入力端子1に印加さ
れた信号がトランジスタ3oのベースに加わる期間では
、入力端子4に印加された信号がトランジスタ33のベ
ースに加わり、また、入力端子2に印加された信号がト
ランジスタ3oのベースに加わる期間では、入力端子3
に印加された信号がトランジスタ33のベースに加わる
。A specific example of the circuit shown in FIG. 3 is shown in FIG. Similarly to Figure 3, apply four types of signals to input terminals 1, 2, 3.4, and
Let us consider the case where a switching pulse with a duty of 50% is applied to 1. When the level of this switching pulse is higher than the voltage determined by the division ratio of resistor 37.38, transistor 17.19 is turned on, transistors 16 and 20 are turned off, and the signal applied to input terminal 1 is applied to the base of transistor 30. join. At the same time, transistors 23 and 25 are also turned off.
It enters the N state and the signal applied to the input terminal 4 is applied to the base of the transistor 330. On the other hand, if the level of the switching pulse is lower than the voltage determined by the division ratio of the resistor 37.38, conversely, transistors 16 and 20°22.27 are in the ON state, transistors 17 and 19°23.25 are in the OFF' state, and the input The signals applied to terminals 2 and 3 are transmitted to transistor 30.
.. Each will be added to 33 bases. Therefore, the signals applied to the input terminals 1 and 2 are applied to the base of the transistor 30, and the signals applied to the input terminals 4 and 3 are applied to the base of the transistor 33 alternately by the switching pulses applied to the respective terminals 11. join. However, during the period in which the signal applied to input terminal 1 is applied to the base of transistor 3o, the signal applied to input terminal 4 is applied to the base of transistor 33, and the signal applied to input terminal 2 is applied to the base of transistor 3o. In the period when it is added to the base, input terminal 3
The signal applied to is applied to the base of transistor 33.
さて、端子11に与えられた切換パルスは移相器14に
て90度位相がずれろうこのノ(ルスレベルが抵抗42
.43の分割比で決まる電圧よりも高い場合はトランジ
スタ29.31がON状態、トランジスタ28.32が
OFF状態となり、トランジスタ3oのベースに加わっ
た信号が端子1゜に出力される。すなわち、この期間の
前半では入力端子1に印加された信号が、後半では入力
端子2に印加された信号が出力される。一方、移相器1
4を通ったパルスのレベルが抵抗42 、43の分割比
で決まる電圧より低い場合はトランジスタ28.32が
ON状態、トランジスタ29 、31がOFF状態とな
り、トランジスタ33のベースに加わった信号が端子1
0に出力される。すなわち、この期間の前半では入力端
子3に印加された信号が、後半では入力端子4に印加さ
れた信号が出力される。よって、端子10には入力端子
1゜2.3.4に印加された4種類の信号が順次切換え
られて出力されることになる。Now, the phase of the switching pulse applied to the terminal 11 is shifted by 90 degrees at the phase shifter 14, and the pulse level of this pulse is shifted by the resistor 42.
.. When the voltage is higher than the voltage determined by the division ratio of 43, transistors 29 and 31 are turned on, transistors 28 and 32 are turned off, and the signal applied to the base of transistor 3o is output to terminal 1°. That is, in the first half of this period, the signal applied to input terminal 1 is output, and in the second half, the signal applied to input terminal 2 is output. On the other hand, phase shifter 1
If the level of the pulse passing through 4 is lower than the voltage determined by the division ratio of resistors 42 and 43, transistors 28 and 32 are turned on, transistors 29 and 31 are turned off, and the signal applied to the base of transistor 33 is transferred to terminal 1.
Output to 0. That is, in the first half of this period, the signal applied to the input terminal 3 is output, and in the second half, the signal applied to the input terminal 4 is output. Therefore, the four types of signals applied to the input terminals 1, 2, 3, and 4 are sequentially switched and outputted to the terminal 10.
以上の通り本発明によれば、信号切換えに用いる切換パ
ルスはデユーティ5Q%のものでよく、この切換パルス
にて4種類の信号も切換パルスの周期の1/4毎に順次
切換えることができ、回路構成が容易となるものである
。As described above, according to the present invention, the switching pulse used for signal switching may have a duty of 5Q%, and with this switching pulse, four types of signals can be sequentially switched every 1/4 of the period of the switching pulse. This facilitates circuit configuration.
第1図は4つの信号を順次切換見得る従来例の回路図、
第2図は第1図の動作説明のための波形図、第3図は本
発明の一実施例による信号切換口−路のブロック図、第
4図は第3図の動作説明のだめの各部波形図、第6図は
第3図の具体例を示す回路図である。
1.2,3,4・・・・・・信号入力端子、11・・・
・・・切換パルス入力端子、1o・・・・・・出力端子
、12.13.15・・・・・・2信号切換器、14・
・・・・・90度移相器、16〜33・・・・・・トラ
ンジスタ、34〜46・・・・・・抵抗。Figure 1 is a circuit diagram of a conventional example in which four signals can be switched sequentially.
Fig. 2 is a waveform diagram for explaining the operation of Fig. 1, Fig. 3 is a block diagram of a signal switching port-path according to an embodiment of the present invention, and Fig. 4 is a waveform diagram of each part for explaining the operation of Fig. 3. FIG. 6 is a circuit diagram showing a specific example of FIG. 3. 1.2,3,4...signal input terminal, 11...
...Switching pulse input terminal, 1o...Output terminal, 12.13.15...2 signal switch, 14.
...90 degree phase shifter, 16-33...transistor, 34-46...resistor.
Claims (1)
2信号切換器に加えて、デユーティ50%の切換パルス
によって上記2つの2信号切換器に加えられている信号
を切換え、これらの出力を第3の2信号切換器に加えて
、上記切換パルスを90度移相したもので信号を切換え
ることにより、上記第3の2信号切換器より4種類の信
号を切換パルスの周期の1/4毎に順次切換えて出力す
る信号切換回路。Adding two signals of four types to a first two-signal switch and a second two-signal switch, and switching the signals applied to the two two-signal switch by a switching pulse with a duty of 50%, By adding these outputs to the third 2-signal switch and switching the signals using the above-mentioned switching pulse shifted by 90 degrees, 4 types of signals can be output from the 3rd 2-signal switch with the period of the switching pulse. A signal switching circuit that sequentially switches and outputs every 1/4 of the signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP78582A JPS58117726A (en) | 1982-01-05 | 1982-01-05 | Signal switching circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP78582A JPS58117726A (en) | 1982-01-05 | 1982-01-05 | Signal switching circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58117726A true JPS58117726A (en) | 1983-07-13 |
JPH0254696B2 JPH0254696B2 (en) | 1990-11-22 |
Family
ID=11483346
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP78582A Granted JPS58117726A (en) | 1982-01-05 | 1982-01-05 | Signal switching circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58117726A (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52147052A (en) * | 1976-06-02 | 1977-12-07 | Hitachi Ltd | Analogue input signal switching unit |
JPS5395552A (en) * | 1977-01-31 | 1978-08-21 | Matsushita Electric Works Ltd | High speed memory unit |
JPS5483331U (en) * | 1977-11-17 | 1979-06-13 | ||
JPS5518016A (en) * | 1978-07-26 | 1980-02-07 | Hitachi Ltd | Voltage divider |
-
1982
- 1982-01-05 JP JP78582A patent/JPS58117726A/en active Granted
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52147052A (en) * | 1976-06-02 | 1977-12-07 | Hitachi Ltd | Analogue input signal switching unit |
JPS5395552A (en) * | 1977-01-31 | 1978-08-21 | Matsushita Electric Works Ltd | High speed memory unit |
JPS5483331U (en) * | 1977-11-17 | 1979-06-13 | ||
JPS5518016A (en) * | 1978-07-26 | 1980-02-07 | Hitachi Ltd | Voltage divider |
Also Published As
Publication number | Publication date |
---|---|
JPH0254696B2 (en) | 1990-11-22 |
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