JPS62152398A - Pulse motor control circuit - Google Patents

Abstract

PURPOSE:To make it possible to deal with different exciting systems with the same circuit constitution by providing a data selector circuit which selects and outputs the output signal of a pair of bidirectional shift registers. CONSTITUTION:In the case of a monophase exciting system when 'O' is given to an input terminal 8 or when '1' is given to an input terminal 9 as an exciting system signal, a selector S1 of a data selector circuit 4 selects a monophase exciting signal of a resistor R<2> given to B (B1-B4) input and outputs to output terminals 10-13. Then, in the case of two-phase exciting system, to an input terminal 8 '1' is given and to an input terminal 9 '0' is given, while the selec tor S1 selects the two-phase exciting signal of a resistor R1 given to A (A1-A4) input and outputs to output terminals 10-13. Next, n the case of a mono- and two-phase exciting system, '1' is given to both input terminals 8 and 9, the selector S1 outputs A and B inputs alternately in response to the clock signal of an input terminal 7 and outputs a mono- and two-phase exciting signals to output terminals 10-13.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a control circuit for driving a pulse motor.

(Prior Art) Generally known conventional pulse motor control circuits include a one-phase or two-phase excitation method shown in FIG. 10(a) and a one-two phase excitation method shown in FIG. 11(a).

In FIG. 1O(a), the shift register circuit 30 loads one-phase or two-phase initial value data applied to the input lines 31 to 34 in parallel, performs a shift operation in response to the clock signal of the input terminal 35, and operates the shift register circuit 30. 30 output Q0
~ Output one-phase or two-phase excitation signal from Q3 to terminals 38 to 4
Output to 1.

In addition, input signals from input terminals 36 and 37 are applied to control inputs S0 and S to determine the operating mode of shift register circuit 30.

Note that FIG. 10(b) is a diagram showing the relationship between input lines and excitation methods, and FIG. 10(c) is a diagram showing the relationship between control inputs and operation modes.

Next, as for FIG. 11(a), two shift register circuits of FIG. 10(a) are connected in series, and the basic operation is the same as that of FIG. 10(a). Figure (b) shows the relationship between the input line and the excitation method. Further, the signal level signal "1" in FIGS. 10 and 11 indicates a high level, and #Q# indicates a low level.

In this way, the drive methods of pulse motors include one-phase excitation force type,
There are three types: 2-phase excitation force type and 1-2 phase excitation force type, but in the past, when changing the excitation method, it was necessary to change the circuit configuration, which had the disadvantage that it could not be handled with the same circuit.

Although there is a known technology that allows the motor excitation method to be selected from three methods using the same circuit, this known technology requires time to set initial data each time the excitation method is switched. Moreover, it requires an input signal for setting initial data, and has the disadvantage that the number of control B lines increases.

(Purpose) The present invention eliminates the drawbacks of the prior art.The purpose of the present invention is to be able to handle different excitation methods with the same circuit configuration, to be able to drive with the minimum required signal, and to be simple. An object of the present invention is to provide a pulse motor control circuit that can easily share a control circuit for motors having different numbers of phases (for example, a three-phase motor and a four-phase motor) by adding a circuit.

(Configuration) To achieve this object, the present invention includes a pair of bidirectional shift register circuits that can be preset and can output in parallel, a gate circuit that controls the operation mode of the bidirectional shift register circuit, and an excitation method setting signal. a presettable counter circuit that sends a clock pulse to the bidirectional shift register circuit according to the clock pulse, and a data selector circuit that selects and outputs an output signal of the bidirectional shift register circuit based on a clock sending gate signal of the counter circuit. A pulse motor signal set by an excitation method setting signal can be obtained from the data selector circuit.

Hereinafter, each embodiment of the present invention will be described based on the drawings.

FIG. 1(a) shows an embodiment of a control circuit for a four-phase pulse motor according to the present invention. In the figure, a forward/reverse rotation signal at an input terminal 6 and a clock signal at an input terminal 7 are applied to a gate circuit 2 and a counter circuit 3. Excitation system signals at input terminals 8 and 9 are applied to counter circuit 3 and pulse generation circuit 5. The pulse generating circuit 5 generates a pulse signal when the excitation method signal is switched, and inputs it to the OR G13 together with the power reset signal. OR Age-01
The output of 3 is the initial setting of the flip-flop F2 of the gate circuit 2 and the flip-flop F3 of the counter circuit 3.
The signal is input to a gate circuit 2 and a counter circuit 3. The outputs of the OR gates G1 and G2 of the gate circuit 2 are input to the shift register circuit 1 in order to determine the operating mode of the registers R1 and R2 of the shift register circuit 1. Further, the output of the flip-flop F1 is an AND gate G8 of the counter circuit 3 which outputs a shift pulse to the shift register circuit l.
and G9 are inputted to the counter circuit 3 in order to control them. Further, a shift pulse is outputted from the OR gate Gll of the counter circuit 3 to the shift register circuit 1. Next, the register R1 of the shift register circuit 1 outputs the 2-sum dynamic magnetic signal, and the register R2 outputs the 1-sum dynamic 6n signal to the data selector circuit 4. Further, in order to select the output signals of the registers R1 and R2 input to the data selector circuit 4, the output signal of the flip F3 of the counter circuit 3 is input to the control input of the selector S1.

The same figure (b) shows the control signal S of registers R and R2.
, and shows the operation mode according to Sl. In addition, in the same figure (C), the control signal of selector S1 and K
It is a figure which shows the operation mode by b.

Next, the operation will be explained with reference to the waveform diagrams shown in FIGS. 2 to 4.

First, in the case of the l-phase excitation method, a high level (hereinafter referred to as "1") is applied to the input terminal 6 as a normal rotation signal. Next, at time t, a low level (hereinafter referred to as "0#") is applied to the input terminal 8 as an excitation method signal, and "1" is applied to the input terminal 9.

The input signals of input terminals 8 and 9 are input to the pulse generation diagram Pr5, and the excitation method signal changes from "0" to "1" or "1".
A pulse signal is output when the signal changes from "0" to "0".

The pulse signal is applied to one input of OR gate G13, and the other input is applied with a power reset signal generated when the power is turned on. The output of OR gate G13 is the set (S) input of flip-flop F2 and the AN of counter circuit 3.
It is applied to one input of D gates G5 and G7. AN
The normal rotation signal # of input terminal 6 is input to the other input of D gate G7.
1", and a signal #1#' obtained by inverting the inverted signal "0#" at the input terminal 6 by the INV gate G4 is applied to the other input of the AND gate G5. That is, when the rotation is forward, the AND gate G7 performs a logical product, and the #1# signal is applied to the reset (R) input of the flip-flop F3, and when the rotation is reverse, the AND gate
The logical product is taken by the D gate G5, and the flip-flop F3
A "1" signal is given to the set (S) input of.

Therefore, after turning on the power or switching the excitation method when setting the forward rotation direction (after time t1 in Figure 2), the output Q of the flip-flop F2 becomes #1'' as shown in Figure 2 (3), and the output Q of the flip-flop F3 becomes #1'' as shown in Figure 2 (3). The output Q of is also “1” as shown in Fig. 2 (7).
'become. Next, when a clock signal is applied to the input terminal 7, the output Q of the flip-flop F2 shifts the data (D) input at the falling edge (trailing edge) of the first clock signal and becomes "0#". The output of
R game) is applied to one input of Gl and G2, the output of flip-flop F1 is applied to the other input, and the signals (4) and (5) in Fig. 2 are output from OR gates Gl and G2. . The output signals are generated by the control human power S0 and S of each register R1 and R2 of the shift register circuit 1.
, is input to.

Next, flip-flop F3 goes to data (J) input #0"
, since #1'' is given to the data (K) input, the output Q of flip-flop F3 is # even after the clock signal is input.
0#, the output Q maintains #1". The signals of the outputs Q and Q are applied to the first inputs of an AND gate G8 and an AND gate G9, and the outputs Q and Q of the flip-flop F1 are applied to the AND gate). G7 and the second input of AND gate G8, the clock signal of input terminal 7 is applied to the third input, and the excitation method signal of input terminals 8 and 9 is applied to the fourth input. A signal obtained by ANDing is given. Also, a signal obtained by inverting the output of AND gate G6 by INV (inverter) gate G12 is given to AND gate G.
10, and the clock signal of the input terminal 7 is applied to the other.

Therefore, in the case of the 1-sum dynamic magnetic force type, the output of AND gate G6 is #θ', and no clock signal is output from AND gates G8 and G9.
A clock signal is output from gate GIO and OR gate G
Clock (CK) of registers R1 and R2 through ll
given to input.

Next, registers R1 and R2 are applied to the clock (G K) inputs when the first clock signal of FIG. 2 (10) is applied, and the control inputs S0 and S, Since both are "1#" as shown in the figure, the register R
1 and R2 load initialization signals of data (D2° to Dp*) input in parallel.

Therefore, the register R1 receives the initial two-phase excitation signal #1".

#Q#, #Q", #1", and register R2 is initially 1.
Phase excitation signals #lZ#Q'', ``o'', ''.

" is output. From the second clock signal until time t2, the control input S0 is "1#, Sl is #0#, and the data is shifted in the forward direction, and after time t2, the control input S0 is "0". ", Sl becomes #1#, and the data is shifted in the reverse direction. Therefore, the binary dynamic magnetic signals of FIG. 3 (12) to (15) from register R1 are also
2 outputs the sum dynamic magnetic signals shown in FIG. 2 (1G) to (19).

Next, the output of the register R1 is sent to A (A, ~A4) of the selector S1 of the data selector circuit 4, and to the register R
The output of 2 is given to the B (B+ to B4) input of the selector S1. Further, the outputs Q and Q of the flip-flop F3 are input to the control input of the selector S1 and to Kb. Therefore, in the sum dynamic magnetic force equation, is “O”,
Kb becomes 1" and selector S1 becomes B (B, ~B4)
The 1 sum dynamic magnetic signal of the register R2 applied to the input is selected and outputted to the output terminals 10 to 13.

Next, in the case of the two-phase excitation method, #1'' is applied to the input terminal 8, and #O# is applied to the input terminal 9. Other input signals and basic operations are the same as the l-phase excitation method. “1#” is input to the data (J) input and “0#” is input to the data (K) input, so
After inputting the clock signal, the output (Q) maintains #l# and the output (Q) maintains #0#. As a result, the selector S1 of the data selector circuit 4 selects the two-phase excitation body number of the register R1 given to the A (A, to A4) input, and output terminals 10 to 1.
Output to 3.

Next, in the case of the 1-2 phase excitation force type, 1# is applied to both input terminals 8 and 9, and the other input signals are the same as in the 1-phase or 2-phase excitation force type.

Next, after turning on the power or switching the excitation method (after time t in FIG. 4), the flip-flops F2 and R3 perform the same operation as in the case of the one-phase excitation force type until the input terminal 7 input signal is input. When a clock signal is input, flip-flop F3 performs a counter operation and outputs Q and Q.
From this, signals (6) and (7) in FIG. 4 are output. These signals become one input to AND gates G8 and G9.

Next, AND game of input terminals 8 and 9) G6
The output of G8 and G9 also becomes "l", and this signal is also generated by AND gates G8 and G9.

Therefore, during normal rotation until time t2, the flip-flop Fl
"1" to AND gate G8, and AND gate G9
Since #0# is input to
A clock signal is output as shown in (8) in the figure. Time t2
After that, when reversing, reverse the forward rotation and AND game) to 08 #0"
, #1# is input to AND gate G9, so AND
A clock signal is outputted from the gate G9 as shown in (9) in FIG. Also, for AND gate G10 one-man power is AND
Since the "0# signal" which is the inverted "1" signal of the gate G6 by the INV gate G12 is input, the clock signal is AN.
There is no output from D gate GIO. Therefore register R
The signal shown in Figure 4 (8) is input to the clock (CK) inputs of R1 and R2 during forward rotation, and the signal shown in Figure 4 (9) is input during reverse rotation, and register R1 receives the signals shown in Figure 4 (12) to (12) to R2. The register R2 outputs the two-phase excitation body number shown in (15), and the one-phase excitation body number shown in FIG. 4 (16) to (19).

Next, the signal shown in FIG. 4 (6) is input from the flip-flop F3 to the control input of the selector S1, and the signal shown in FIG. 4 (7) is input to the control input Kb. 7, the first clock signal is the A((A+~14) input signal, and the second is the B(
B,~B4) The input signal is outputted thirdly, and the A and B input signals are output alternately, and the output is as shown in Figure 4 (20)~
The 1-2 phase excitation body number of (23) is output to the output terminals 10 to 13.

In the above example, it was explained that the initial value setting of each register of the shift register circuit 1 is performed by the first clock signal of the clock signals applied to the input terminal 7, but the present invention is not limited to this. , for example, when the power is turned on or when switching the excitation method.

In addition, in the case of the 1-2 phase excitation force type, an example of a circuit is such that when forward rotation starts from 2-phase excitation, and when reverse rotation starts from 1-phase excitation, for example, a counter circuit as shown in Figures 8 and 9 is used. 3
Furthermore, by changing a part of the circuit of the shift register circuit 1, it is possible to start with two-phase excitation in both forward and reverse rotation.

Next, as an application of the present invention, by adding a simple circuit to the four-phase motor control circuit shown in FIG. 1, a common control circuit for three-phase motors and four-phase motors can be constructed. An example of the control circuit is shown in FIG.

Explaining FIG. 5, the input signals to the data inputs OS* and I)st of each register are input to the outputs of registers R1 and R2 in the shift register circuit 1, and the 3-phase/4-phase ( Selectors S and S that are controlled by a high level/low level) motor switching signal are added. These S and Sb connect registers R1 and R2, Ds, l and Ql, and DsL and Q when a 3-phase motor is selected, and registers R,, Rg when a 4-phase motor is selected.
Co-DSII and Q, and D! L and Q4 are connected. Other operations of the gate circuit 2, counter circuit 3, data selector circuit 4, input terminals 6 to 9, and output terminals 10 to 13 are the same as in the four-phase motor control circuit shown in FIG. As described above, it is possible to drive a three-phase or four-phase motor by selecting different excitation methods with the same circuit configuration.

As another application, a 5-phase motor control circuit can be constructed by adding a part of the same circuit to the 4-phase motor control circuit shown in FIG. An example of the control circuit is shown in FIG.

In the 4-phase motor shown in Figure 1, there are three excitation methods.
For 5-phase motors, 2-phase, 2-3-phase, 4-phase, 4-5-phase and 5-phase
There are a phase excitation force type and six types of excitation methods. Therefore, in the 5-phase motor control circuit shown in FIG. 6, the excitation system signal that requires 3 manpower, which is one more manpower than the 4-phase motor control circuit shown in FIG.
given to 10. These three human-powered excitation system signals are applied to the decoder circuit 11, where they are converted into the six excitation system signals and output. The correspondence between the output and excitation method is the 7th
It will look like the figure. Next, the shift register circuit has a configuration of four 5-output registers, R1 to R4, and the data selector circuit 4 has a configuration of two 5-output selectors, Sl and S2, and at the same time, the excitation signal output terminals are also 21 and 10
Become an individual. Other input terminals 6 and 7, gate circuit 2 and counter circuit 3 are the same as the four-phase motor control circuit shown in FIG. Therefore, since the operation is the same as above, 6 excitation methods can be selected for driving a 5-phase motor with a simple circuit configuration.

(Effects) The present invention is as described above, and according to the pulse motor control circuit according to the present invention,
It is possible to provide a motor control circuit that can be handled using the same circuit configuration.

[Brief explanation of drawings]

FIG. 1(a) is a control circuit diagram of a four-phase pulse motor according to an embodiment of the present invention, FIG. 3 and 4 are waveform diagrams of each part of the l-phase, 2-phase, and 1-2 phase excitation dynamic magnetic force, respectively. FIG. 5 is a control circuit diagram according to the second embodiment, and FIG. 6 is a diagram of the third embodiment. The control circuit diagram according to the embodiment, FIG. 7 is a diagram showing the relationship between the decoder output and the excitation method, FIG. 8 is a detailed diagram of the counter circuit, FIG. 9 is a detailed diagram of the shift register circuit, and FIG. 11(b) and ('C) are diagrams showing the excitation method and operation mode, and FIG. 11(a) is a diagram showing the main part of a pulse motor control circuit according to a conventional example. A diagram showing the main parts of the pulse motor control circuit, the same figure (
b) is a diagram showing an excitation method. ■...Shift register, 2...Gate circuit, 3...
- Counter circuit, 4... data selector circuit. Figure 2'#4 (19) 000 l O'l 000 and ~r') size 0■■■〇-~n ;:2;;;:;~Sasasa $ -8--e-Imahi Figure 8] Light Figure 9

Claims (1)

[Claims] A pair of bidirectional shift register circuits that can be preset and can output in parallel; a gate circuit that controls the operating mode of the bidirectional shift register circuit; and a gate circuit that sends clock pulses to the bidirectional shift register circuit in accordance with an excitation method setting signal. It has a presettable counter circuit and a data selector circuit that selects and outputs the output signal of the bidirectional shift register circuit based on the clock transmission gate signal of the counter circuit, and the data selector circuit selects and outputs the output signal of the bidirectional shift register circuit using the clock transmission gate signal of the counter circuit. A pulse motor control circuit that is characterized by being able to obtain a pulse motor signal that is controlled by the pulse motor.