JPS60249418A - Output driving circuit - Google Patents

Output driving circuit

Info

Publication number
JPS60249418A
JPS60249418A JP10679484A JP10679484A JPS60249418A JP S60249418 A JPS60249418 A JP S60249418A JP 10679484 A JP10679484 A JP 10679484A JP 10679484 A JP10679484 A JP 10679484A JP S60249418 A JPS60249418 A JP S60249418A
Authority
JP
Japan
Prior art keywords
output
circuits
circuit
drive circuit
enable signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10679484A
Other languages
Japanese (ja)
Inventor
Takao Tosaka
登坂　高夫
Makoto Morishita
誠 森下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10679484A priority Critical patent/JPS60249418A/en
Publication of JPS60249418A publication Critical patent/JPS60249418A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/62—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors

Landscapes

  • Electronic Switches (AREA)

Abstract

PURPOSE:To reduce the transient variation of a load, a wiring, and a power source due to impedance by setting operation delay times different from one another to driving circuits of output circuits which are arranged in parallel for the power source. CONSTITUTION:AND gates 31-3n and inverters 21-2n are provided for driving plural output circuits 11-1n by signals IN1-INn. Delay circuits 11 and 12 are provided between a common enable signal input terminal ENL and proper input terminals of AND gates 31-3n, and output circuits are divided to circuits, which are operated early when an enable signal is impressed, and circuits which are operated late then. Consequently, even in case that all outputs are changed from the low level to the high level when the enable signal is impressed to the terminal ENL, half outputs are first changed from the low level to the high level, and left outputs are changed from the low level to the high level after a delay, and the output current from the power source is changed from ''1'' to 1/2 and 0 successively when the same loads are used as loads 11-1n; and thus, the variation of the power source is reduced, and the transient variation of loads is reduced.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は大電流、電圧を扱う出力駆動回路に係シ、特に
この種の出力駆動回路のＩＣ化にあたって出力スイッチ
時の過渡応答特性の改善を図ることができる出力駆動回
路に関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an output drive circuit that handles large currents and voltages, and in particular, it is an object of the present invention to improve the transient response characteristics at the time of output switching when converting this type of output drive circuit into an IC. The present invention relates to an output drive circuit that can be used in various ways.

〔従来技術〕[Prior art]

従来の出力駆動回路の一例を第１図に示し説明すると、
図において、ｖｃは電源（電源電圧）、ＩＮｌ、ＩＮｚ
　・・・・ＩＮｎ−ｔ　、ＩＮｎは入力信号、ＥＮＬは
イネーブル信号、ｖｏは出力電圧、■。は出力電流を示
す。１１．１２　・・・Ｉｎ−１＋１ｎは出力駆動回路
、３１．３２　・・・３ｎ−Ｉｔ３ｎはイネーブル信号
ＥＮＬ　と入力信号ＩＮｒ。An example of a conventional output drive circuit is shown in FIG. 1 and explained as follows.
In the figure, vc is the power supply (power supply voltage), INl, INz
...INn-t, INn is an input signal, ENL is an enable signal, vo is an output voltage, ■. indicates the output current. 11.12...In-1+1n is an output drive circuit, 31.32...3n-It3n is an enable signal ENL and an input signal INr.

ＩＮｚ　・・・ｌＮｎ−１，ＩＮｎをそれぞれ入力とし
これら各入力の論理積をとるアンドゲートで、このアン
ドゲート３Ｉ〜３ｎの出力端はそれぞれ出力駆動回路２
１〜２ｎと負荷１１〜１ｎを直列に介して電源■。に接
続されている。そして、電源ｖｃに対して並列に接続さ
扛た各出力回路の負荷１１〜１ｎを出力駆動回路２１〜
２ｎが入力信号ｌＮ５＝ＩＮｎによつ“Ｃそれぞれ駆動
するように構成されている０ このように構成された出力駆動回路において、入力側に
接続されたアンドゲート３１〜３ｎによつてイネーブル
信号ＥＮＬの入力、ＪｐＬ／ｒ　の場合には、すべて出
力は気Ｈ〃となり、出力の負荷１１〜１ｎをそ牡ぞれ駆
動しない状態にする。このとき、いま、すべての出力が
％Ｌ／／の状態でイネーブル信号ＥＮＬが気Ｈ〃から％
Ｉ、／／へ変化したとすると、例えば、出力電圧Ｖ。と
出力電流■。は出力回路の出力電流電圧特性を示す説明
図である第２図のように変化する。すなわち、電圧は上
昇。INz is an AND gate that takes INn-1 and INn as inputs and takes the AND of these inputs, and the output terminals of the AND gates 3I to 3n are connected to the output drive circuit 2.
1 to 2n and loads 11 to 1n in series. It is connected to the. Then, the loads 11 to 1n of the output circuits connected in parallel to the power supply VC are connected to the output drive circuits 21 to 1n.
In the output drive circuit configured in this way, the enable signal ENL is driven by the AND gates 31 to 3n connected to the input side. In the case of the input, JpL/r, all outputs become H and the output loads 11 to 1n are not driven.At this time, all outputs are now %L//. In the state, the enable signal ENL changes from H to %.
For example, if the output voltage changes to I, //, then the output voltage V. and output current■. changes as shown in FIG. 2, which is an explanatory diagram showing the output current-voltage characteristics of the output circuit. In other words, the voltage increases.

電流は減少の方向へ動き、出力は第２図のｂのターンオ
フの線に沿って変化する。ここで、負荷１貫〜１ｎが純
抵抗で電源のインピーダンスも十分に小さいときは破線
にて示すａの直線上を動くが、配線の長い場合、誘導性
負荷の場合、電源の出力インピーダンスが大きい場合な
どは電流と電圧の変化に位相差が生じ出力回路に過大な
負担となる。なお、Ｃはターンオフの線を示し、ＶＣは
電源電圧を示す。The current moves in a decreasing direction and the output changes along the turn-off line of FIG. 2b. Here, when the load 1-1n is a pure resistance and the impedance of the power supply is sufficiently small, it will move on the straight line a shown by the broken line, but if the wiring is long or the load is inductive, the output impedance of the power supply will be large. In some cases, a phase difference occurs between changes in current and voltage, placing an excessive burden on the output circuit. Note that C indicates a turn-off line, and VC indicates a power supply voltage.

第３図はこの第１図の出力駆動回路を用いた具体例を示
す回路図で、シリアル入力データをパラレルデータに変
換して出力するシフトレジスタ・ラッチ付のドライブ回
路の一例を示すものである。Figure 3 is a circuit diagram showing a specific example using the output drive circuit shown in Figure 1, and shows an example of a drive circuit with a shift register and latch that converts serial input data into parallel data and outputs it. .

この第３図において第１図と同一部分には同一符号を付
して説明を省略する。ＬＣＨはラッチ入力、Ｓ工Ｎは入
力信号、Ｔはトリガ入力を示し、０ＵＴ１，０ＵＴ２．
０ＵＴ３　・・・・０ＵＴｎ−１。In FIG. 3, the same parts as in FIG. 1 are given the same reference numerals, and their explanation will be omitted. LCH is a latch input, S-N is an input signal, T is a trigger input, and 0UT1, 0UT2.
0UT3...0UTn-1.

０ＵＴｎはそれぞｎ出力を示す。0UTn each indicates n outputs.

２１　．２２　．２３　・・・２ｎ−ρとそれぞれ出力
駆動回路、３１　！　３２　＋　３３　・・・３ｎ−１
＋３１はそれぞれアンドゲートで、これら出力駆動回路
２１〜２ｎおよびアントゲ−）３＋　〜３ｎはそれぞｎ
第１図に示す出力駆動回路２１〜２ｎおよびアンドゲー
ト３１〜３ｎに対応する。’１＋’２＋４３　・・・・
４ｎ−１＋’ｎはラッチ回路、５、。21. 22. 23...2n-ρ and output drive circuits, respectively, 31! 32 + 33...3n-1
+31 are AND gates, and these output drive circuits 21 to 2n and ant gates 3+ to 3n are each n.
This corresponds to the output drive circuits 21 to 2n and the AND gates 31 to 3n shown in FIG. '1+'2+43...
4n-1+'n is a latch circuit, 5.

５２．５３　・・・・５ｎ−ｔ、５ｙｌは縦続接続さ扛
たＤ型クリップフロップでこｎらはシフトレジスタを構
成している。なお、６，７・・・・１０ｔｉ−すれぞれ
バッファを示す。52.53 . . . 5n-t and 5yl are D-type clip-flops connected in cascade, and these constitute a shift register. Note that 6, 7, . . . , 10ti- each indicate a buffer.

そして、シフトレジスタを構成するＤ型フリップフロッ
プ５１〜５ｎの各Ｔ端子にはトリガ入力Ｔがバッファ９
を介してそれぞれ入力され、Ｄ型フリップフロップ５１
のＤ端子には入力信号ＳＩＮがバッファ８を介して入力
され、Ｑ端子からの出力はＤ型フリップフロップ５２の
Ｄ端子に導かれると共にラッチ回路４１のＤ端子に導入
されるように構成さ扛ている。また、Ｄ型りリップ７日
ツブ５ｚのＱ端子からの出力はＤ型フリップフロップ舷
３のＤ端子に導かれると共にラッチ回路４２のＤ端子に
導入されるように構成され、以下、Ｄ型フリップフロッ
プ５３〜５ｎおよびラッチ回路４３〜４ｎは上記と同様
にそれぞれ関連接続されている。ここで、ラッチ回路４
１〜４ｎの各り端子にはラッチ入力ＬＣＨがバッファ７
を介してそれぞれ入力されている。A trigger input T is connected to each T terminal of the D-type flip-flops 51 to 5n constituting the shift register.
are inputted through the D-type flip-flop 51.
The input signal SIN is inputted to the D terminal of the circuit via the buffer 8, and the output from the Q terminal is guided to the D terminal of the D-type flip-flop 52 and also introduced to the D terminal of the latch circuit 41. ing. Further, the output from the Q terminal of the D-type lip 7-day lug 5z is configured to be guided to the D terminal of the D-type flip-flop side 3 and introduced to the D terminal of the latch circuit 42. The latch circuits 53 to 5n and the latch circuits 43 to 4n are connected in relation to each other in the same manner as described above. Here, latch circuit 4
The latch input LCH is connected to the buffer 7 for each terminal from 1 to 4n.
Each is input via .

そして、アンドゲート３１〜３ｎはそれぞれイネーブル
信号ＥＮＬと各ラッチ回路４１〜４ｎの各Ｑ端子からの
出力を入力とし両人力の論理積をとり、その各出力端か
らそれぞれ出力駆動回路２１〜２Ｔｌ　を通して出力０
ＵＴｓ〜０ＵＴＴ１を得るように構成されている。The AND gates 31 to 3n each input the enable signal ENL and the output from each Q terminal of each latch circuit 41 to 4n, perform a logical product of both, and pass the output drive circuits 21 to 2Tl from their respective output terminals. Output 0
It is configured to obtain UTs~0UTT1.

このように構成されたドライノ（−回路において、Ｄ型
フリップフロップ５１〜５ｎの縦続接続よりなるシフト
レジスタは入力信号ＳＩＮの情報をトリガ入力Ｔからの
クロックに応じて、順次ビットに転送して、１時的に情
報を蓄積し、ラッチ回路４１〜４ｎにおいてはシフトレ
ジスタの出力である情報をとらえて、そ牡を保持し、ア
ンドゲート３１〜３ｎにおいてはこの各ラッチ回路４１
〜４ｎの各出力とイネーブル信号ＥＮＬとの論理積をと
り、その各出力によってそれぞれ出力駆動回路２１〜２
ｎをドライブし、その各出力端からは出力ＯＵ　Ｔ　１
〜０ＵＴｎがそれぞれ得られる。In the Draino(-) circuit configured in this manner, a shift register consisting of cascaded D-type flip-flops 51 to 5n sequentially transfers the information of the input signal SIN to bits in accordance with the clock from the trigger input T. Information is temporarily accumulated, and the latch circuits 41 to 4n capture and hold the information that is the output of the shift register, and the AND gates 31 to 3n each latch circuit 41.
The logical product of each output of ~4n and the enable signal ENL is taken, and each output drives the output drive circuits 21 to 2.
n, and output OUT 1 from each output terminal.
~0UTn are obtained, respectively.

しかしながら、このような出力駆動回路においては、前
述したように、配線の長い場合や誘導性負荷の場合、電
源の出力インピーダンスが大きい場合などには電流と電
圧の変化に位相差が生じ、出力回路に過大な負担となる
という欠点があった。However, in such an output drive circuit, as mentioned above, when the wiring is long, there is an inductive load, or the output impedance of the power supply is large, a phase difference occurs between the changes in current and voltage, and the output circuit The disadvantage was that it placed an excessive burden on

〔発明の概要〕[Summary of the invention]

本発明は以上の点に鑑み、このような問題を解決すると
共にかかる欠点を除去すべくなされたもので、その目的
は簡単な構成によって、出力電流の変動を小さくシ、負
荷、配線、電源のインピーダンスに起因する過渡変動を
小さくすることができ、大電流・電圧を取扱う出力駆動
回路のＩＣ化にあたって出力スイッチ時の過渡応答特性
の改善を図ることができる出力駆動回路を提供すること
にある。In view of the above points, the present invention has been made to solve such problems and eliminate such drawbacks.The purpose of the present invention is to minimize fluctuations in output current with a simple configuration, and to reduce load, wiring, and power supply. An object of the present invention is to provide an output drive circuit that can reduce transient fluctuations caused by impedance and improve transient response characteristics during output switching when implementing an output drive circuit that handles large currents and voltages into an IC.

このような目的を達成するため、本発明は、共通のイネ
ーブル入力端子からの信号が出力駆動回路を起動または
停止させるまでに要する時間、すなわち、動作遅延時間
が上記出力駆動回路によって互いに異なるように、遅延
回路を上記共通のイネーブル入力端子と駆動回路との間
に配置するようにしたものである。To achieve this object, the present invention provides a method in which the time required for a signal from a common enable input terminal to start or stop the output drive circuit, that is, the operation delay time is different depending on the output drive circuit. , a delay circuit is arranged between the common enable input terminal and the drive circuit.

〔発明の実施例〕[Embodiments of the invention]

以下、図面に基づき本発明の実施例を詳細に説明する。 Embodiments of the present invention will be described in detail below based on the drawings.

第４１祉本発明による出力駆動回路の一実施例を示す回
路図である。FIG. 41 is a circuit diagram showing an embodiment of an output drive circuit according to the present invention.

この第４図において第１図と同一符号のものは相当部分
を示し、１１．１２はそれぞれイネーブル信号ＥＮＬが
印加される共通のイネーブル入力端子とアントゲ−）３
１．３ｎ−ｔの各入力端との間にそれぞれ配置さｎた遅
延回路で、この遅延回路１１，１２は、共通のイネーブ
ル入力端子からの信号が出力駆動回路２ｘ、２１−ｔを
起動または停止させるまでに要する時間、すなわち、動
作遅延時間が出力駆動回路によって互いに異なるように
構成されている。そして、この遅延時間発生用のゲート
（遅延回路）はずべてのアンドゲートの入力に追加せず
、一部だけ、すなわち、早く動作する回路と遅ｎて動作
する回路に分けている０例えば、奇数番の出力回路に遅
延ゲートである遅延回路を付加し、偶数番目の出力回路
には付加しないなどの取沙汰めを行うように構成されて
いる。In FIG. 4, the same reference numerals as in FIG.
The delay circuits 11 and 12 are arranged between the input terminals of the output drive circuits 2x and 21-t respectively. The time required to stop the output drive circuit, that is, the operation delay time, is configured to be different depending on the output drive circuit. Then, this gate (delay circuit) for generating delay time is not added to the input of all the AND gates, but only some of them are divided into circuits that operate quickly and circuits that operate slowly.For example, The configuration is such that a delay circuit, which is a delay gate, is added to odd-numbered output circuits, and not added to even-numbered output circuits.

つぎにこの第４図に示す実施例の動作を説明する０ 上記のように、遅延回路１１．１２は早く動作する回路
と遅れて動作する回路に分けて配置されているので、例
えば、すべての出力が％Ｌ〃の状態の場合であっても、
まず、半分の出力が′ＬＩから気Ｈ〃へ変化し、遅れて
残りの出力がゝＩｔ　”から％Ｈ”　へ変化となシ、す
べての負荷１１〜１ｎが接続されている電源ｖｃから出
力電流の変化をみると、すべての負荷１１〜１ｎが同じ
場合には１→竹→０のように変化する。Next, we will explain the operation of the embodiment shown in FIG. Even if the output is at %L,
First, half of the outputs change from ``LI'' to ``H'', and after a delay, the remaining output changes from ``It'' to %H''. Looking at the change in current, when all the loads 11 to 1n are the same, the current changes as 1→bamboo→0.

これは、電源の変動が小さくすむことを意味し、したが
って、出力回路部での弁荷変動も小さいことを意味する
。This means that fluctuations in the power supply are small, and therefore valve load fluctuations in the output circuit are also small.

そして、負荷が純抵抗で、電源のインピーダンスも十分
に小さいときには直線上（第２図ａ参照）を動くが、配
線、有限の電源インピーダンスの影響によって直線から
負荷線がずれ、過大な電圧・電流が出力にかかることを
説明している出力回路の出力電流・電圧特性図である第
２図の負荷線の抵抗の場合からのずれが小さくなり、こ
れは出刃回路の耐量負荷が小さくてよいことを意味する
０このように、出力電流の変動が小さくなシ、負荷、配
線、電源のインピーダンスに起因する過渡変動を小する
ことができ、これによって、出力回路に耐量が小さいよ
うなトランジスタを用いることができる。When the load is a pure resistance and the impedance of the power supply is sufficiently small, it moves in a straight line (see Figure 2 a), but due to the influence of the wiring and finite power supply impedance, the load line deviates from the straight line, causing excessive voltage and current. The deviation from the case of the resistance of the load line in Figure 2, which is an output current/voltage characteristic diagram of the output circuit that explains that the voltage is applied to the output, is small, and this means that the withstand load of the Deba circuit can be small. 0 In this way, it is possible to reduce fluctuations in the output current and to reduce transient fluctuations caused by the impedance of the load, wiring, and power supply. be able to.

第５図はこの出力駆動回路を用いた具体例を示す回路図
で、この出力回路の適用例を説明するためのシリアル入
力データをパラレルデータに変換して出力するシフトレ
ジスタ・ラッチ付のドライバー回路の一例を示すもので
ある。Figure 5 is a circuit diagram showing a specific example using this output drive circuit, and is a driver circuit with a shift register and latch that converts serial input data into parallel data and outputs it to explain an application example of this output circuit. This is an example.

この第５図において第３図と同一部分には同一符号を付
して説明を省略する。第３図と異なる点は、バッファ６
の出力端とアントゲ−）３＋。In FIG. 5, the same parts as in FIG. 3 are given the same reference numerals, and their explanation will be omitted. The difference from Figure 3 is that the buffer 6
output end and ant game) 3+.

３３　．３ｎ−１の各入力端との間に遅延時間発生用の
ゲートである遅延回路１１，１２．１３をそｔぞれ配置
したことにある。33. This is because delay circuits 11, 12, and 13, which are gates for generating delay time, are respectively arranged between the input terminals of the circuit 3n-1.

このように、動作遅延時間が出力駆動回路によって異な
るように遅延回路を配置することによシ、大電流・電圧
を取扱う出力駆動回路のＩＣ化にあたって出力スイッチ
時の過渡応答特性の改善を図ることができる０ 〔発明の効果〕 以上の説明から明らかなように、本発明によれば、複雑
な手段を用いることなく、共通のイネープル入力端子と
１駆動回路との間に遅延回路を設けた簡単な回路構成に
よって、出力電流の変動が小さくなり、負荷、配線およ
び電源のインピーダンスに起因する過渡変動を小さくす
ることができ、これによって出力回路に１ｌＩｉｔ盾の
小さいようなトランジスタを使えるようになったので、
実用上の効果は極めて犬である。また、大電流・電圧を
取扱う出力駆動回路のＩＣ化にあたって、出力スイッチ
時の過渡応答特性の改善を図ることができるという点に
おいて極めて有効である。In this way, by arranging delay circuits so that the operation delay time differs depending on the output drive circuit, it is possible to improve the transient response characteristics at the time of output switching when converting an output drive circuit that handles large currents and voltages to an IC. [Effects of the Invention] As is clear from the above explanation, according to the present invention, a delay circuit can be provided between a common enable input terminal and a drive circuit without using complicated means. This circuit configuration reduces fluctuations in the output current and reduces transient fluctuations caused by load, wiring, and power source impedance, which makes it possible to use transistors with small shields in the output circuit. So,
The practical effect is quite dogmatic. Furthermore, when implementing an output drive circuit that handles large currents and voltages into an IC, the present invention is extremely effective in that it is possible to improve transient response characteristics during output switching.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の出力駆動回路の一例を示す回路図、第２
図は動作り兄明に供する出力回路の出力電流・電圧特性
を示づ説明図、第３図は第１図に示す出力駆動回路の適
用例を説明するためのドライバー回路、第４図は本発明
による出力駆動回路の一実施例を示す回路図、第５図は
第４図に示す出力駆動回路の適用例を説明するだめのド
ライバー回路である。 ２１〜２ｎ　・・・・出力駆動回路、３１〜３ｎ・・・
・アンドゲート、１１〜１３・・・・遅延回路。 代理人　大　岩　増　雄 第１図 第２図 第　４　図 −工　２ Ｚ　（Ｊ　−）− １）　」　のFigure 1 is a circuit diagram showing an example of a conventional output drive circuit;
The figure is an explanatory diagram showing the output current/voltage characteristics of the output circuit used for operation. Figure 3 is a driver circuit for explaining an application example of the output drive circuit shown in Figure 1. Figure 4 is an illustration of the main output circuit. FIG. 5 is a circuit diagram showing one embodiment of the output drive circuit according to the invention, and is a driver circuit for explaining an application example of the output drive circuit shown in FIG. 4. 21~2n...output drive circuit, 31~3n...
-AND gate, 11-13...delay circuit. Agent Masuo Oiwa Figure 1 Figure 2 Figure 4 - Engineering 2 Z (J -) - 1)

Claims (1)

【特許請求の範囲】[Claims] 電源に対して多数並列に配置された出力回路と、この出
力回路をそれぞれ駆動する駆動回路のそれぞれ独立した
入力端子とは別にすべての前記駆動回路を同時に起動ま
たは停止の制御を行う共通のイネーブル信号入力端子と
をもつ出力駆動回路において、前記共通のイネーブル信
号入力端子と前記駆動回路との間に、前記共通のイネー
ブル信号入力端子からの信号が前記出力駆動回路を起動
または停止させるまでに要する動作遅延時間が該出力駆
動回路によって互いに異なるように遅延回路を配置した
ことを特徴とする出力駆動回路。In addition to multiple output circuits arranged in parallel to the power supply and independent input terminals of the drive circuits that drive each of these output circuits, a common enable signal that simultaneously controls the start or stop of all the drive circuits. In an output drive circuit having an input terminal, an operation required for a signal from the common enable signal input terminal to start or stop the output drive circuit is provided between the common enable signal input terminal and the drive circuit. An output drive circuit characterized in that delay circuits are arranged so that delay times differ from one another depending on the output drive circuit.
JP10679484A 1984-05-24 1984-05-24 Output driving circuit Pending JPS60249418A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10679484A JPS60249418A (en) 1984-05-24 1984-05-24 Output driving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10679484A JPS60249418A (en) 1984-05-24 1984-05-24 Output driving circuit

Publications (1)

Publication Number Publication Date
JPS60249418A true JPS60249418A (en) 1985-12-10

Family

ID=14442793

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10679484A Pending JPS60249418A (en) 1984-05-24 1984-05-24 Output driving circuit

Country Status (1)

Country Link
JP (1) JPS60249418A (en)

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