JPS58116736A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS58116736A
JPS58116736A JP21209281A JP21209281A JPS58116736A JP S58116736 A JPS58116736 A JP S58116736A JP 21209281 A JP21209281 A JP 21209281A JP 21209281 A JP21209281 A JP 21209281A JP S58116736 A JPS58116736 A JP S58116736A
Authority
JP
Japan
Prior art keywords
film
gas
spacer
spacer film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21209281A
Other languages
Japanese (ja)
Inventor
Yorihiro Uchiyama
内山 順博
Kazunari Shirai
白井 一成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21209281A priority Critical patent/JPS58116736A/en
Publication of JPS58116736A publication Critical patent/JPS58116736A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching

Abstract

PURPOSE:To accurately form a micro-miniature pattern by forming a spacer film and gas shielding film on a semiconductor substrate, forming a film by patterning and by removing said film from the substrate through generation of gas from the spacer film. CONSTITUTION:A spacer film 2 which decomposes when gas is exhausted is formed on a semiconductor substrate 1 by a low temperature annealing. Then, a gas shielding film 3 which prevents transmission of gas is formed thereon. Next, the gas shielding film and spacer film 2 are patterned with a photo resist film 4 used as the mask and thereby a film 5 is formed on the entire part thereof. Thereafter, gas is generated from the spacer film 2 by the low temperature annealing and thereby the spacer film 2, gas shielding film formed thereon and the film 5 formed thereon are removed from the substrate 1.

Description

【発明の詳細な説明】 本発明は、被膜のパターニングをリフト・オフ法で行な
う工程が含まれている半導体装置の製造方法の改良に関
する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for manufacturing a semiconductor device that includes a step of patterning a film by a lift-off method.

従来、リフト・オフ法を実施する材料としてはフォト・
レジスト膜を使用することが多い。即ち、半導体基板上
にパターニングされたフォト・レジスト膜を形成し、そ
の上に被膜を形成し、フォト・レジスト膜を溶解するこ
とに依ってその上の被膜とともに除去し、該被膜のパタ
ーニングを行なうようにしている。
Traditionally, the material used to perform the lift-off method is photo-fluorescence.
A resist film is often used. That is, a patterned photoresist film is formed on a semiconductor substrate, a film is formed on it, the photoresist film is removed together with the film above it by dissolving it, and the film is patterned. That's what I do.

ところで、前記被膜を形成するには蒸着法を適用するこ
とが多いが、その際に加熱を必要とするので、その熱で
フォト・レジスト膜が変形し、微細パターンが得られな
い欠点がある。
Incidentally, the vapor deposition method is often applied to form the film, but this requires heating, which has the disadvantage that the photoresist film is deformed by the heat, making it impossible to obtain a fine pattern.

本発明は、フォト・レジスト膜を使用する場合と比較す
ると工程は若干増加するが微細パターンを確実に形成で
きるリフト・オフ法を提供し、高密度の半導体装置を容
易に製造できるようにするもので69、以下これを詳細
に説明する。
The present invention provides a lift-off method that can reliably form fine patterns, although the number of steps is slightly increased compared to the case where a photoresist film is used, and makes it possible to easily manufacture high-density semiconductor devices. 69, which will be explained in detail below.

第1図乃至第41は本発明一実施例を説明する為の工程
要所に於ける半導体装置の畳部断面図であり、次に、こ
れ等の図を参照しつつ記述する。
1 to 41 are cross-sectional views of a folding portion of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and the following description will be made with reference to these figures.

第1図参照 (1)  半導体基板1上に厚さ例えば1〜2〔μm〕
程度のポリイミド樹脂からなるスペーサ膜2を形成する
。ポリイミド樹脂を塗布するにはスピン・コート法を適
用することができる。
Refer to Fig. 1 (1) The thickness is, for example, 1 to 2 [μm] on the semiconductor substrate 1.
A spacer film 2 made of a polyimide resin of about 30% is formed. A spin coating method can be applied to apply the polyimide resin.

尚、スペーサ膜2はポリイミド樹脂のみでなく、温度4
0G(C)程度以上に加熱された際にガスを放出する材
料であって、半導体装置自体或いは製造工程に悪影響を
及はさないものであれば何を使用しても嵐い。
Note that the spacer film 2 is not only made of polyimide resin, but also has a temperature of 4.
Any material can be used as long as it emits gas when heated to about 0 G (C) or higher and does not have a negative effect on the semiconductor device itself or the manufacturing process.

(2)  例えば化学気相成長法にて窃化シリコンから
なるガス遮断膜3を厚さ例えば3000 (又〕程度に
形成する。
(2) A gas barrier film 3 made of recycled silicon is formed to a thickness of, for example, about 3,000 mm by, for example, chemical vapor deposition.

このガス遮断膜3は窒化シリコンに限らず、緻密であっ
て、スペーサ膜2から発生するガスの透過を妨げ得る材
料であって、半導体装置自体或いは製造工程に悪影響を
与えないものに代替することができる。
The gas barrier film 3 is not limited to silicon nitride, but may be replaced with a material that is dense and can block the permeation of the gas generated from the spacer film 2, and that does not adversely affect the semiconductor device itself or the manufacturing process. I can do it.

(3)  フォト・リソグラフィを実施する為のフォト
・レジスト膜4を形成する。
(3) Form a photoresist film 4 for performing photolithography.

第2図参照 (4)  フォト・レジスト膜4をマスクにしてガス遮
断面膜3及びスペーサ膜2をパターニングする。
Refer to FIG. 2 (4) Using the photoresist film 4 as a mask, the gas barrier film 3 and the spacer film 2 are patterned.

尚、この際の工、ツチングは尖鋭なパターンを得る為に
はドライ・エツチング法を採用すれば良い。
In this case, a dry etching method may be used to obtain a sharp pattern.

第3図参照 (5)蒸着法にて例えば二酸化シリコンからなる被膜5
を厚さ例えば5000〜aooo〔b程度に形成する。
See Figure 3. (5) A coating 5 made of silicon dioxide, for example, by vapor deposition.
is formed to a thickness of, for example, about 5,000 to aooo [b].

この際、フォト・レジメ11は図示の如く残しても良い
し、除去しても良い。また、被膜5としては二酸化シリ
コンの他にアルミニウム等の金属や種々の材料を適用で
きる。
At this time, the photo regimen 11 may be left as shown in the figure, or may be removed. Further, as the film 5, other than silicon dioxide, metals such as aluminum and various other materials can be used.

第4図参照 (6)  温度410(C)程度の熱処理を加える。こ
れに依夛、ポリイミド樹)のスペーサ膜2からはガスが
発生する。しかし、このガスはガス遮断膜3で抑えられ
るので外方に発散する量は少ない。
Refer to Figure 4 (6) Heat treatment is applied at a temperature of about 410 (C). Due to this, gas is generated from the spacer film 2 (made of polyimide wood). However, since this gas is suppressed by the gas barrier membrane 3, only a small amount of the gas emanates outward.

従って、スペーサ膜2には高いガス圧が加わるようにな
シ、遂には自分自身を持ち上げるような状態になって基
板1から剥離してしまう。このとき、その上のガス遮断
膜3、フォト・レジスト膜4、被膜5も一同時に除去さ
れ、所謂、リフト・オフ法に依るパターニングが行なわ
れるものである。
Therefore, a high gas pressure is applied to the spacer film 2, which eventually lifts itself up and peels off from the substrate 1. At this time, the gas barrier film 3, photoresist film 4, and film 5 thereon are also removed at the same time, and patterning is performed by the so-called lift-off method.

前記実施例では二酸化シリコンの被膜5を蒸着(或いは
スペッタ)で形成する際の温度が約200〔C〕であシ
、ポリイミド樹脂のスペーサ膜2は410(C’1未満
の温度では変形しないので所定パターンのリフト・オフ
・パターニングが可能である。まえ、エツチングはドラ
イ・エツチングに限らず、ウェット・エツチングに依る
ことも可能であシ、その場合、サイド・エツチングは不
可避であるが、実際上の不都合は殆んど生じない。これ
を第5図及び第6図を参照しつつ説明する。
In the above embodiment, the temperature at which the silicon dioxide film 5 was formed by vapor deposition (or sputtering) was about 200 [C], and the polyimide resin spacer film 2 did not deform at a temperature below 410C (C'1). Lift-off patterning of a predetermined pattern is possible.Etching is not limited to dry etching, but can also rely on wet etching.In that case, side etching is unavoidable, but in practice This will hardly cause any inconvenience.This will be explained with reference to FIGS. 5 and 6.

ms図参照 (1)  第1図の状態でウェット・エツチングを行な
い、マスクとして使用したフォト・レジスト4を除去す
ると第5図に見られるようにスペーサ膜2がサイド・エ
ツチングされた構造でパターニングされる。
Refer to the ms diagram (1) When wet etching is performed in the state shown in Figure 1 and the photoresist 4 used as a mask is removed, the spacer film 2 is patterned in a side-etched structure as seen in Figure 5. Ru.

ここで、窒化シリコンのガス遮断膜3のエツチング方法
としてはCFaガスによるドライエッチを、また、ポリ
イミド樹脂のスペーサ膜2のエツチング液としてはヒド
ラジンを使用することができる。
Here, dry etching using CFa gas can be used as an etching method for the silicon nitride gas barrier film 3, and hydrazine can be used as an etching solution for the polyimide resin spacer film 2.

第6図参照 (2)  第3図に関して説明した工程と同様にして被
膜5を形成する。
See FIG. 6 (2) The coating 5 is formed in the same manner as the process explained with reference to FIG.

(3)  この後、第4図に関して説明した工程と同様
にして被膜5のパターニングを行なう。
(3) After this, patterning of the coating 5 is performed in the same manner as in the process explained with reference to FIG.

以上の説明で判るように、本発明に依れば、半導体基板
上に400(C)程度以上の低温アニールで脱ガス分解
するスペーサ膜とその上に該ガスの透過を妨げるガス遮
断膜を形成して、それを更にその上に形成される被膜の
り7ト・オフ用材料として使用しているので、そのリフ
ト・オフされる被膜を形成する際の温度に充分耐えるこ
とができ、フォト・レジスト族をり7ト・オフ用材料と
して使用した場合のようなパターンの変形は発生しない
から、高密度の半導体装置を製造するのに有効である。
As can be seen from the above explanation, according to the present invention, a spacer film that degass and decomposes by low-temperature annealing at about 400 (C) or higher is formed on a semiconductor substrate, and a gas barrier film that prevents the permeation of the gas is formed on the spacer film. Since it is used as a material for the film to be lifted off, it can withstand the temperature required to form the film to be lifted off, and the photoresist is This method is effective in manufacturing high-density semiconductor devices because pattern deformation does not occur when the group is used as a chip-off material.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第4図は本発明一実施例を説明する為の工程
要所に於ける半導体装置の要部断面図、第5図及び第6
図は他の実施例を説明する為の工程要所に於ける半導体
装置の要部断面図である。 図に於いて、lは基板、2はスペーサ膜、3はガス遮断
膜、4はフォト・レジスト膜、5は被膜である。 特許出願人 富士通株式会社 代理人弁理士 玉 蟲 久 五 部 (外3名)第1図 第2図 第3図
1 to 4 are cross-sectional views of main parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and FIGS.
The figure is a sectional view of a main part of a semiconductor device at key points in the process for explaining another embodiment. In the figure, 1 is a substrate, 2 is a spacer film, 3 is a gas barrier film, 4 is a photoresist film, and 5 is a coating film. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Hisa Gobe Tamamushi (3 others) Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に低温アニールに依9脱ガス分解するスペ
ーサ膜とその上に該ガスの透過を妨げるガス遮断膜を形
成し、次に、それ等ガス遮断膜及びス、ペーサ膜をパタ
ーニングしてから全面に被膜を形成し10次に、前記低
温アニールを行なって前記スペーサ膜からガスを発生さ
せ該スペーサ膜とその上のガス遮断膜と更にその上の被
膜とを前記半導体基板から除去する工程が含まれてなる
ことを特徴とする半導体装置の製造方法。
A spacer film that is degassed and decomposed by low-temperature annealing is formed on the semiconductor substrate, and a gas barrier film that prevents the permeation of the gas is formed thereon, and then the gas barrier film and the spacer film are patterned. A step of forming a film on the entire surface and then performing the low temperature annealing to generate gas from the spacer film and removing the spacer film, the gas barrier film thereon, and the film thereon from the semiconductor substrate. A method of manufacturing a semiconductor device, comprising:
JP21209281A 1981-12-30 1981-12-30 Preparation of semiconductor device Pending JPS58116736A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21209281A JPS58116736A (en) 1981-12-30 1981-12-30 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21209281A JPS58116736A (en) 1981-12-30 1981-12-30 Preparation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS58116736A true JPS58116736A (en) 1983-07-12

Family

ID=16616735

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21209281A Pending JPS58116736A (en) 1981-12-30 1981-12-30 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS58116736A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02259622A (en) * 1988-11-08 1990-10-22 Nokia Unterhaltungselektronik Deutsche Gmbh Covering of base body panel for liquid crystal cell

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02259622A (en) * 1988-11-08 1990-10-22 Nokia Unterhaltungselektronik Deutsche Gmbh Covering of base body panel for liquid crystal cell

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