JPS5811587B2 - digital beam form - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to digitization of a beamformer that realizes beam formation of a phased array used in sonar and the like.

Conventionally, beamformers for receivers have been of an analog type using a tapped analog delay line and a summing amplifier, or of a digital type using a shift register and an adder. Waveform distortion occurs due to wires, miniaturization is difficult,
In addition, the latter requires a large number of output taps of the shift register, so an LSI-based shift register cannot be used, and a large number of ICs are required, resulting in increased power consumption.

In addition, Japanese Patent Publication No. 43-14911 describes a method for realizing a similar function using an electronic computer, but it uses random access memory (hereinafter abbreviated as RAM) used in ordinary electronic computers as a delay element. For this purpose, the delay time is specified by the memory address, but each time new data is input, the relationship between the delay time and the memory address must be changed, and this change takes a considerable amount of time, which increases processing speed. It doesn't matter.

Also, in order to avoid this address change, it is possible to create a program in advance for all combinations of addresses that need to be changed, but this has disadvantages such as the amount of programming becomes enormous and it is not economical. There is.

In order to solve these drawbacks, the present invention uses a RAM as a delay element, a counter that advances at a cycle equal to the sampling cycle of the input signal, and a read-only memory (hereinafter referred to as ROM) that stores the relationship between the tap number and the sensor number. A desired beam is formed by controlling the RAM and changing the delay time using the address calculated from the output of The present invention realizes a beamformer that can be applied to various sonars with sensor arrays of different sizes and shapes by simply changing the program, requires a small amount of programs, and is easy to create.

FIG. 1 is a block diagram showing the functions of a beamformer that the present invention is trying to realize, and 1-1.1-2.・
..., 1- has input terminals corresponding to 2 sensors, 2-
1.2-2. ..., 2- is a tapped delay line, 3-1
．． 3-2. ..., 3- is an attenuator, 4 is an adder, and 5 is an output terminal.

Here, a system consisting of an input terminal 1-1, a tapped delay line 2-1, an attenuator 3-1, an adder 4, and an output terminal 5 constitutes a transversal filter for one sensor output signal, and the beamformer can be considered to be the sum of these transversal filters.

Note that if it is necessary to form a large number of beams with different orientations, a large number of the circuits shown in FIG. 1 may be used in parallel, but in this case, tapped delay lines 2-1, 2-2. ...,
2- can be shared.

Further, normally, the number of attenuators connected to one tapped delay line is one per beam output, and there are cases where all the attenuators have the same gain (no shading).

FIG. 2 is a diagram showing an embodiment of the present invention, and 1-1.1
-2. ..., 1- is an input terminal, 5 is an output terminal, 6 is a multiplexer, 7 is an A/D converter, 8 is an input buffer, 9 is a RAM, 10 is a multiplier, 11 is an adder, 12 is a register , 13 is an output buffer, 14 is a RAM address generator, 15 is a zero address counter, 16 is a table memory, 17 is a table memory counter, 18 is a start address table, 19 is a program memory, and 20 is a program memory counter.

Here, input terminals 1-1.1-2. ..., 1-k are time-division multiplexed by a multiplexer 6, converted into digital codes by an A/D converter 7, and temporarily stored in an input buffer 8.

On the other hand, the program memory 19 contains an input command W, a beam forming command BF, a beam number B0. B1. ..., a return instruction is written as shown in FIG. 3, and its address is given by the program memory counter 20,
The contents are sequentially read out and sent to the start address table 18.

The start address of the table memory 16 corresponding to each instruction is stored therein, and by loading that value into the table memory counter 17, the table memory in which the microprogram and table corresponding to one instruction are stored is stored. Read out the parts sequentially from the first address.

The table memory 16 is normally a read-only memory (hereinafter abbreviated as ROM), but it can read the input buffer 8, write to the RAM 9, load and reset the register 12, write to the output buffer 13, and clock the zero address counter 15. , a 0 section storing microinstructions that control loading and clocking the table memory counter 17, clocking and clearing the program memory counter, an n section representing the tap number of the transversal filter, an n section representing the sensor number, and an attenuator section. It consists of a W part that stores weights, and in response to an input command, the k part contains (0, 1,...k-1), the n part contains all zeros, and the c part stores the input buffer readout and A RAM write command is written, and the relationship between the sensor number, tap number, and weight for the specified beam number is written in the register 12 and output buffer 13 in the k, n, and w parts, respectively, in response to the beam forming command. Control instructions are written in part 0.

The following Table 1 shows an example of instructions written in the table memory 16.

Here, the number of sensors was set to -16.

#0 to #15 of table memory 16 (0th address to 15th address)
microinstruction and data corresponding to the input instruction W at address), microinstruction and data corresponding to the beamforming instruction BF and Bo at #16 to #31, beamforming instruction BF to #32 to #47, and beamforming instruction BF to B1. Corresponding microinstructions and data are written.

Here, the 6th part of the microinstruction reads the input buffer 8 and writes it to the RAM 9 for the input instruction W.
For beam forming command BF, read RAM9,
The output of the W portion of the table memory 16 is multiplied by the multiplier 10 and added to the contents of the register 12 using the adder 11. In the SOM and the last step, the added result is sent to the output buffer 13 and the register 12 is cleared. This means 0UTPUT.

Further, CK in the sixth section is a clock signal that increments the zero address counter 15, and is used only at the beginning of the input command W.

Additionally, the zero address counter 15 is incremented by one step before an input command or at the end of an input command, and the program memory counter 20 is incremented by one step at the end of each command, and the start address table 1 is added to the table memory counter 17.
Load the output of 8.

The RAM address generator 14 has a cello address counter 1.
From the output of 5 and the n part of the table memory to the output of RA
It generates the address of M9 and has the configuration shown in FIG. 4a or 4b.

Here, 14-1 is an input terminal from the zero address counter 15, 14-2 and 14-3 are input terminals from the outputs of the n part and the n part of the table memory 16, respectively, and 21
is a mod N subtracter (where N is the tapped delay line 2-1, 2-2, etc. in FIG. 1).

2 - the number of taps), 22 and 23 are multipliers that output N and N times their inputs (where K is the number of sensors), 24 is an adder, 14-4 is an output terminal,
Based on the output of the zero address counter 15, which is an N-ary counter, calculate and output the address of the RAM where the signal corresponding to the output signal of the n-th tap of the tapped delay line for the second sensor is stored. do.

Using FIG. 4a, the N words of signals input from one sensor are stored in a portion of RAM 9 with successive addresses, and using FIG. 4b, they have every other word of address in RAM 9. In each case, RAM 9 requires a capacity of KXN words.

The following Table 2 shows the memory division of the RAM 9 in a matrix representation when the RAM address generator 14 of FIG. 4b is used.

In Table 2, for example, the output signal of the 0th sensor is written to addresses #0, #K, . . . , #KW-K of the RAM 9.

In that case, since the tap number n in the input command W is 0, the address classification is specified only by the output of the zero address counter 15, and the output of the zero address counter 15 stores the latest data in the memory area of this range. It shows the street address.

Therefore, if the output of the address counter 15 is now i, the address category i corresponds to the 0th tap of each delay line 2-1 to 2-2 in FIG. 1, and the correspondence between the address category and the tap number is The relationships are as shown in Table 3 and are determined by relative relationships.

Furthermore, as will be described later, the address classification in the beam forming command BF is specified using the tap number based on the output of the zero address counter 15, so that the address classification corresponding to the tap number is designated.

Here, when N or K is an insole of 2, the operation of multiplying by N or 2 is realized by a simple shift, and the adder 24 is not required.

Therefore, it is a good idea to use Figure 4a when N is in the middle of 2, and use Figure 4b when K is in the middle of 2, but in the former, the address classification is specified using the sensor number as the upper bit, and zero This is a case where the address order within the address classification is specified by using the value obtained by changing the value of the address counter 15 by the tap number as the lower bit, and the latter is a case where the relationship between the upper bit and lower bit is simply reversed. Both perform the same function.

Now, when the input commands are executed in FIG. 2, that is, when the micro-instructions corresponding to the input command W are read out sequentially from the table memory 16, the RAM add generator 14 generates the zeroth An address in the RAM 9 corresponding to the tap is generated, and an input signal from the input gate unit 8 is written into the address portion of the RAM 9.

Next, when the beam forming command BF is executed, the table memory 16 sequentially generates the tap number n and weight w necessary for forming the beam of the designated number for the sensor number k, and the RAM addon generator 14 generates an address in RAM 9 corresponding to this sensor number and tap number n, reads out the signal stored in the part with this address in the output of RAM 9, and outputs this signal and table memory 1.
The multiplier 10 calculates the product with the weight w read out from the w part of 6, and the adder 11 and the register 12 accumulate the products to calculate the output signal corresponding to the designated beam, and the output signal is sent to the output buffer 13. The needle will fit once.

This output signal is read out from the output buffer 13 to the output terminal 5 as required.

In this way, each instruction written in the program memory 19 is executed in the order in which it is written, and several beam outputs are calculated sequentially.

When the last instruction written in the program memory 19 is executed, a pulse is applied to the clear terminal of the program memory counter 20 by the return instruction, and the program returns to the first instruction in the program memory 19.

By repeating such operations, it is possible to simultaneously form multiple beams while inputting periodically sampled signals.

Here, the sampling frequency fs for the output signal of each sensor
is usually chosen to be 5 to 6 times the highest frequency of the input signal in order to suppress the loss due to the roughness of the tag spacing, but since it is sufficient for the output of the beamformer to satisfy the usual sampling theorem, Depending on the signal bandwidth, the beamformer output signal samples can be decimated by a factor of 2 or even less.

Therefore, when thinning out to 1/2, for example, it is sufficient to perform each beam forming process once in response to two input commands, as shown in FIG.

One input command inputs one sample of each sensor's output signal, so if the average time interval at which input commands are executed is shorter than the sampling period 1/fs, the sampling frequency f
Beamforming processing of the sensor output signal sampled at s is possible.

Therefore, if high-speed components are used, a large number of beams can be formed with one beamformer.

Note that in FIG. 2, the contents of the second part of the table memory 16 can easily be generated by a counter, since normally adjacent addresses within one instruction differ by at most 1. , the capacity of the table memory 16 can also be saved.

Furthermore, it goes without saying that various commonly used methods can be used to convert the sensor output signal into a digital code, and it is also possible to convert the output signal into an analog signal using a D/A converter using conventional techniques. It can be easily achieved.

As described above, since RAM is used as the tapped delay line, connection lines corresponding to each tap output can be omitted, and LSI R
By using AM, the number of ICs can also be significantly reduced.

It also has the advantage that it can be used for sensor arrays of different shapes by rewriting the contents of the program memory and table memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the functions of the beamformer realized by the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is an example of instructions written to the program memory in FIG. 4a and 4b are block diagrams illustrating the contents of the RAM address generator of FIG. 2. DESCRIPTION OF SYMBOLS 1... Input terminal, 5... Output terminal, 6... Multiplexer, 7... A/D converter, 8... Input buffer, 9... RAM, 10... Multiplier, 11... Adder, 12... Shimisuta, 13... Output buffer,
14...RAM address generator, 15...Zero address counter, 16...Table memory, 17...
Table memory counter, 18... Start address table, 19... Program memory, 20... Program memory counter, 21... Subtractor, 22...
- Multiplier, 23... Multiplier, 24... Adder.

Claims (1)

[Claims] 1. The number of sensors is N, and the number of taps is N.
A random access memory 9 capable of storing word sensor outputs, and a microprogram corresponding to an input command written using a number of addresses, each address having a specific tap number and a predetermined sensor number. A table memory 16 in which a microprogram corresponding to a beam forming command is written using a plurality of addresses, and each address stores a predetermined tap number and a predetermined sensor number; means 17-2 for sequentially reading out the microprogram corresponding to the input command or beam forming command from the table memory for each address;
0, a zero address counter 15 that is incremented at a cycle equal to the sampling cycle of the sensor according to an input command, and an address of the random access memory 9 that is specified by associating each N word of the same sensor number with a consecutive address. an address generator that specifies words for each tap number of the same tap number in correspondence with successive addresses, the first counter 15
The second counter 16 generates an address code based on a value changed by a tap number read from a table memory 17 and a value read from a second counter 16. digital beamformer.