JPS58115836A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS58115836A JPS58115836A JP56210993A JP21099381A JPS58115836A JP S58115836 A JPS58115836 A JP S58115836A JP 56210993 A JP56210993 A JP 56210993A JP 21099381 A JP21099381 A JP 21099381A JP S58115836 A JPS58115836 A JP S58115836A
- Authority
- JP
- Japan
- Prior art keywords
- metal plate
- semiconductor element
- opening
- area
- fixed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
＜１＞ 発明の技術分野
本発明は半導体装置に関し、特にセラミνりを主体とす
る半導体装置用パッケージの構成に関する０
（２）従来技術と問題点
半導体素子特に半導体集積回路素子を収容するプーアル
インライン減セラミックパッケージは、従来一般に第１
図に示される構成を有している。Detailed Description of the Invention <1> Technical Field of the Invention The present invention relates to a semiconductor device, and in particular to the structure of a package for a semiconductor device mainly made of ceramic material. (2) Prior art and problems Semiconductor elements, especially semiconductor integrated In the past, in-line reduced-ceramic packages that house circuit elements generally
It has the configuration shown in the figure.
同図（ａ）は気密封止用蓋部材が固着されていない状態
を示し、伽）は（ａ）のムーＡ′断面を示す。FIG. 5(a) shows a state in which the hermetic sealing lid member is not fixed, and FIG. 3(a) shows a cross section of FIG.
同図において、１１ａセラミック基体、１２は前記セラ
ｔｙり基体に設けられ九半導体素子収容用開口、１３は
前記開口１２の底部に配設され導電層を兼ねる金属化（
メタライズ）層、１４は前記金属化層１３上にろう材に
よって固着された金属板、１５は前記開口１２の周縁部
に配設され導電層を構成する金属化層、１６は前記セｌ
ｉｔり基体１１の周縁部に訃いて前記金属化層１３．１
５の延長部にろう付は等によシ接続された外部接続端子
である◇
ｆｆＦ、ｌ ７Ｆｉ苧導体集積回路素子であハ前記金属
板１４上にろう材によシ固着される。そして、腋半導体
素子１７の電極ｈｖ−ド１ｉ１８にょシ金属化層ｌｓの
各々に接続される。更に咳半導体素子１７嬬前記開口１
２を覆う蓋部＃（図示せず）によって気密封止される。In the figure, 11a is a ceramic base, 12 is an opening provided in the ceramic base for accommodating a semiconductor element, and 13 is a metallization (13) provided at the bottom of the opening 12, which also serves as a conductive layer.
14 is a metal plate fixed on the metallized layer 13 with a brazing material; 15 is a metallized layer disposed around the periphery of the opening 12 and constitutes a conductive layer;
The metallized layer 13.1 is applied to the periphery of the substrate 11.
External connection terminals are brazed to the extended portions of 5 and 7Fi conductor integrated circuit elements, and are fixed onto the metal plate 14 using a brazing material. The electrodes HV-1 and 18 of the armpit semiconductor element 17 are connected to each of the metallized layers Is. Furthermore, the opening 1 of the semiconductor device 17 is
2 is hermetically sealed by a lid # (not shown).
ここで前記金属化層１３は例えばタングステンに）等か
ら形成され、その表出部表面には工Ｖケル（Ｎ１）メッ
キが施される。また前記金属［１４は主面にニッケルメ
ッキが施され九篭すプデン（Ｍｏ）から構成され、銀（
Ａｇ）ろう等のろう材によｐ前記金属化層１３上に固着
される。Here, the metallized layer 13 is formed of, for example, tungsten), and the exposed surface of the metallized layer 13 is plated with nickel (N1). Further, the metal [14] is composed of nickel-plated main surface (Mo), and silver (
Ag) It is fixed onto the metallized layer 13 by a brazing material such as a wax.
を九外部接続端子１６は、コパール等から構成される。The external connection terminal 16 is made of copper or the like.
このような構造を有するセラ＜Ｖタパッケージにおいて
、前記七ツ電ツク基体１１に設けられる半導体素子収容
用開口１２及び、かかる開口１２に収容されその底部に
固着畜れる金属板１４社、従来第２図に示される加電状
態で固着されている。In a cellar package having such a structure, the opening 12 for accommodating a semiconductor element provided in the seven-power switch base 11, and the metal plate accommodated in the opening 12 and fixed to the bottom thereof are manufactured by 14 companies. It is fixed in the energized state shown in Figure 2.
このため、かかる金属板１４を前記金属化層１３上に固
着した＊に、金属［１４の狭量から金属化１
層１３の露出表面に連続するニッケルメッキ層（
下地メッキ）２１及び金（ムＵ）ノブキ層２２を形成し
ようとする際に１前記金属Ｉ［１４と開口１２０内側面
との近接あるいは接触１１においては、かかるいは接触
によって閉じ込められ九空気の存在によって、前記ニッ
ケルメッキ及び金メツ中が所望の厚さに施されない状態
を生じ、を九かかるめつき丸環の後の洗浄処理の際に拡
かかる洗浄が十分になされないという状態を生じてしま
う。For this reason, the metal plate 14 is fixed on the metallized layer 13, and the metallized layer 14 is
A continuous nickel plating layer (
When attempting to form the base plating 21 and the gold layer 22, in the proximity or contact 11 between the metal I[14 and the inner surface of the opening 120, air is trapped by the contact or is trapped. Due to its presence, the nickel plating and gold plating may not be applied to the desired thickness, and the cleaning process after the nickel plating and gold plating may not be done sufficiently. Put it away.
したがりて、前記金属板１４上に半導体素子を固着する
際の加熱飽現によって、主として金属板１４の前記下地
ニッケルメッキ層２１に酸化あるいは拡散による変質、
変色を生じ腐蝕を生じ島くなりてしオう０かかる下地ニ
ッケルメツ中層２１の腐蝕によって、かかる金属板上に
固着される半導体素子の性能の低下並びに寿命の低下を
招来してしまう。Therefore, due to heating saturation when a semiconductor element is fixed on the metal plate 14, the base nickel plating layer 21 of the metal plate 14 is mainly subjected to deterioration due to oxidation or diffusion.
This corrosion of the underlying nickel metal intermediate layer 21, which causes discoloration, corrosion, and formation of islands, leads to a decrease in the performance and life of the semiconductor element fixed on the metal plate.
なお第２図において、前記８１図に示される部位と対応
する部位には、同じ数字、符号を付している。そして、
２３は前記金属化層１３の表ｉ１に予め形成されたニッ
ケルメッキ層、２４は銀ろう勢のろう材、２５．２６’
は金属板１４の主面に形成され九−シケルメッキ層であ
る。In FIG. 2, parts corresponding to those shown in FIG. 81 are given the same numbers and symbols. and,
23 is a nickel plating layer previously formed on the surface i1 of the metallized layer 13; 24 is a silver brazing filler metal; 25.26'
is a nine-layer plating layer formed on the main surface of the metal plate 14.
（３）発明の目的
本発明はこのような従来のセ２建ツクパッケージの有す
る欠点を除去して、半導体素子固着部におけるめりき不
良、更にはこれに基づく半導体素子の特性、寿命の低下
を生ずることのないセラ電ツクパッケージ構造を有する
半導体装置を提供しようとするものである。(3) Purpose of the Invention The present invention eliminates the drawbacks of the conventional double-walled package, and eliminates plating defects in the part where the semiconductor element is fixed, as well as the deterioration of the characteristics and life of the semiconductor element due to this. It is an object of the present invention to provide a semiconductor device having a ceramic package structure that does not cause this problem.
（４）発明の構成
このため、本発明によれば、半導体素子を収容する略矩
形状の半導体素子収容用開口を有する絶縁物基体、前記
開口の底部に配設された略矩形状の金属板、前記金属板
ｊに搭載、固着された半導体素子、前記絶縁物基体の周
囲に配設された外部接続端子、前記半導体素子の電極と
前記外部接続端子とを電気的Ｋｍ続する導電部材とｔ有
する半導体装置において、前記金属板は、前記絶縁物基
体への固着面の面積が前記半導体素子の固着面Ｏ面積よ
シも大とされてなる半導体装置が提供される０
（５）発明の実施例
以下本発明を実施例をもりて詳細に説明する。(4) Structure of the Invention Therefore, according to the present invention, there is provided an insulator base having a substantially rectangular semiconductor element accommodating opening for accommodating a semiconductor element, and a substantially rectangular metal plate disposed at the bottom of the opening. , a semiconductor element mounted and fixed on the metal plate j, an external connection terminal disposed around the insulator base, a conductive member electrically connecting the electrode of the semiconductor element and the external connection terminal by Km; In the semiconductor device, the area of the surface of the metal plate fixed to the insulating substrate is larger than the surface area O of the surface fixed to the semiconductor element. (5) Implementation of the Invention EXAMPLES The present invention will now be described in detail with reference to Examples.
第３図は本発明によるセ９＜ｖクパッケージの要部、す
なわちセラ（ｙり基体に設けられる半導体素子収容用開
口と、かかる開口に収容されその底部に固着される金属
板の固着状態を示している。FIG. 3 shows the main parts of the cell package according to the present invention, that is, the opening for accommodating a semiconductor element provided in the cellar base, and the fixing state of the metal plate accommodated in the opening and fixed to the bottom thereof. It shows.
同図（ｂ）は同図（＆）の変形例を示す。The figure (b) shows a modification of the figure (&).
同図において３１．１２ａ本発明にかかる金属板を示す
・前記第２図に示される部位と対応する部位には同じ数
字を付している。In the figure, 31.12a shows a metal plate according to the present invention. The same numbers are attached to the parts corresponding to those shown in FIG. 2 above.
すなわち、本発明によれば、セラ建ツクパッケージ基体
１１に設けられ九半導体素子収容用開口１２の底部に固
着される金属板３１あるいは３２社、セラ建ツク基体１
１への固着面（下面）すなわち金属化層１３表面のニッ
ケルメッキ層２３への固着間の面積が、半導体素子１７
の搭載固着面α面）の面積よシも大とされる。したがり
て、かかる金属板３１あるいは３２の側面は全周にわ九
シ傾斜面を有し、かかる金属板３１あるいは３２の断面
線略台形を有する。That is, according to the present invention, the metal plate 31 or 32 provided in the ceramic package base 11 and fixed to the bottom of the semiconductor element accommodating opening 12,
1, that is, the area between the surface of the metallized layer 13 and the nickel plating layer 23 is
It is also said that the area of the mounting fixation surface (alpha surface) is larger than that of the mounting surface (alpha surface). Therefore, the side surface of the metal plate 31 or 32 has a sloping surface around the entire circumference, and the cross section of the metal plate 31 or 32 has a substantially trapezoidal shape.
このような形状の金属板の適用によｐ％該金属板をセラ
Ｚ １１り基体の半導体素子収容用開口の底部に固着し
た際、かかる金属板の側面と半導体装このため、かかる
金属板３１あるいは３２が半導体素子収容用開口１２内
の金属化層上に固着される際にかかる金属板３１の中心
と開口の中心とが一致しなくても、を九かかる金属板３
１が開口１２の内側面に当接することになっても、金属
板３１このように金属板３１の側面部と半導体素子収容
用開口１２の内側面が十分に広い間隙を有しているため
、かかる金属板３１を前記開口１２内の金属化層に固着
した後に１金属板の表面から金属化層の露出表面に連続
するニッケルメッキ層及び金メッキ層を形成しようとす
る＠に、金属［８１の１ｉ１１ＦＩｉ部と開口１２０内
側面との関にメツ中処鳳液が容易に侵入し得、よって所
望の厚さのメツ中層を形成することがで勤る０またかか
るメッキ嶋理後に洗浄処理の際にも金属板の側面部と開
口の内側面との間に洗浄液が容易に侵入して、洗浄処理
を確実に行なうことができる。By applying a metal plate having such a shape, when the metal plate is fixed to the bottom of the opening for accommodating a semiconductor element in the Cera Z 11 substrate, the side surface of the metal plate and the semiconductor element are connected to each other. Alternatively, even if the center of the metal plate 31 and the center of the opening do not coincide when the metal plate 32 is fixed onto the metallized layer in the semiconductor element housing opening 12, the metal plate 3
1 comes into contact with the inner surface of the opening 12, the metal plate 31 has a sufficiently wide gap between the side surface of the metal plate 31 and the inner surface of the semiconductor element housing opening 12. After fixing the metal plate 31 to the metallized layer in the opening 12, the metal [81 1i11FIi part and the inner surface of the opening 120 can easily be penetrated by the coating solution, thereby forming a coating layer with a desired thickness. Also, during the cleaning process after such plating process. Also, the cleaning liquid can easily enter between the side surface of the metal plate and the inner surface of the opening, so that the cleaning process can be performed reliably.
し九がりて前記金属板上に半導体素子を固着する加熱逃
理がなされてｔ１前記ニッケルノブキ層に変質、変色を
生じない。更にかかるメッキ層に変質を生じないことか
ら、かかる金属板上に搭載、固着されゐ半導体素子に性
能の低下、寿命の低下等を招来することがなく、半導体
装置としての製造歩留）、信頼性を高めることができる
。In addition, a heat escape is provided to fix the semiconductor element on the metal plate, so that no deterioration or discoloration occurs in the nickel wood layer at t1. Furthermore, since the plating layer does not undergo any deterioration, there is no deterioration in the performance or lifespan of the semiconductor elements mounted and fixed on the metal plate, thereby increasing the manufacturing yield and reliability of the semiconductor device. You can increase your sexuality.
本発明にかかる金属板の加工方法の実施例を第４図に示
す。同図において４１はＶｉｌ１４２を施し個々に分離
する前の金属板、４３はエア吸着治具、４４．４４’は
押圧による固定保持具、４５は磁気吸着治具を示す。An embodiment of the metal plate processing method according to the present invention is shown in FIG. In the figure, reference numeral 41 indicates a metal plate before Vil142 is applied and the metal plate is separated into individual parts, 43 indicates an air adsorption jig, 44 and 44' indicate a fixing holder by pressing, and 45 indicates a magnetic adsorption jig.
同図−）は、ニッケルめっきを施した金属板にＶ溝加工
を行なった状態の乎面、同図（ｂ）は葎）ＯＢ −Ｂ′
断面を示しこの状態でチョコレートブレークといわれる
方法で分離する場倉會示す０同図（ｃ）は金属板をエア
によ〉吸着、同図（２）は抑圧固定保持具、同図（＠）
は磁気によシ吸漕して分離されるまで加工する場合を示
し、いずれの場合もＶ形のカッター、砥石などを用いて
加工するが放電加工によって同様に加工してもよい。な
お加工の際生じ九パリはバレル研磨などの方法Ｋｌ除去
するとよい。(-) is the surface of a nickel-plated metal plate with a V-groove machined, and (b) is the surface of the nickel-plated metal plate.
The cross section is shown, and in this state, the metal plate is separated by a method called chocolate break.The same figure (c) shows the metal plate being adsorbed by air, the same figure (2) shows the suppressing fixing holder, and the same figure (@).
shows the case where the parts are machined by magnetic suction until they are separated; in either case, a V-shaped cutter, a grindstone, etc. are used for processing, but it is also possible to perform the same processing by electrical discharge machining. Incidentally, it is preferable to remove the particles generated during processing by a method such as barrel polishing.
なお前記実施例では、デュアルインツイン製セラミック
パッケージを掲げて説明したが、本発明はこれに限られ
るものではなく、フラット臘、チップキャリア、ビンア
レイなどのタイプでも、半導体素子を収容する丸めの凹
部を形成しその底部に金属板を銀ろうなどくよ〉固着す
る構造を有する半導体装置用パッケージであれば適用す
ることができる。Although the above embodiments have been described using a dual-in-twin ceramic package, the present invention is not limited to this, and can also be applied to a rounded recess for accommodating a semiconductor element in a type such as a flat lug, a chip carrier, or a bin array. The present invention can be applied to any semiconductor device package having a structure in which a metal plate is firmly fixed to the bottom of the package, such as silver solder.
又、金属板は通常、熱伝導性、熱膨張係数等の面から一
般には前述の如く篭すプデン板が使用されるが、鉄ニツ
ケル合金、鉄ニツケルコバルト合金、ｉｓなども使用す
ることができる。In addition, as for the metal plate, generally, from the viewpoint of thermal conductivity, coefficient of thermal expansion, etc., a metal plate is generally used as described above, but iron-nickel alloy, iron-nickel-cobalt alloy, IS, etc. can also be used. .
（６）発明Ｏ効果
以上のように装置９１１によれば、セラｔｙクパッケー
ジの半導体素子固着部におけるめ−）ｔｋ不良。(6) Effects of the Invention As described above, according to the device 911, there is no tk defect in the semiconductor element fixing portion of the ceramic package.
更にはこれに基づく半導体菓子の特性の低下、寿命の低
下を招くことのないセラ々ツクバックージ構造が得られ
る。Furthermore, based on this, it is possible to obtain a ceramic bag structure that does not cause a deterioration in the properties or the lifespan of semiconductor confectionery.
４、図面の筒塔なｉｉｇ男
第１図は半導体装置用デ轟アルインライン歴パッケージ
の構造を示す平面図（ａ）及び断面図伽）、第２図は従
来の半導体装置用パッケージにおける半導体素子収容用
開口と、該開口内に配設される金属板との固着状態を示
す要部断面図、第３図は本発明の半導体装置用パッケー
ジにおける半導体素子収容用開口と金属板との固着状態
を示す要部断面図、第４図は本発明にかかる金属板の加
工方法の実施例を示す正面図およびｒｒｍ図である。4. Figure 1 is a plan view (a) and a cross-sectional view showing the structure of a conventional in-line package for semiconductor devices, and Figure 2 is a diagram showing the semiconductor element in a conventional package for semiconductor devices. A sectional view of a main part showing the state of adhesion between the accommodating opening and the metal plate disposed in the opening, and FIG. 3 shows the state of adhesion between the semiconductor element accommodating opening and the metal plate in the semiconductor device package of the present invention. FIG. 4 is a front view and an RRM view showing an embodiment of the metal plate processing method according to the present invention.
図において、１１・・・・・−・セラ建ツク基体１２・
・・・・−・・半導体素子収容用開口１４、３１．３２
・・−・・金属板
１７・・・・・・・・・・・・・・−・・・・・・・・
半導体凧子。In the figure, 11...- Ceramic construction base 12.
......Semiconductor element housing opening 14, 31.32
・・・・Metal plate 17・・・・・・・・・・・・・・・・・・・・・・・・・
Semiconductor kite.
Claims (1)
を有する絶縁物基体、前記開口の底部に配設された略矩
形状の金属板、前記金属板上に搭載、固着された半導体
素子、前記絶縁物基体の周囲に配設された外部接続端子
、前記半導体素子の電極と前記外部接続端子とを電気的
に接続する導電部材とを有する半導体装置において、前
記金属板は、前記絶縁物基体への固着面の面積が前記半
導体素子の固着面の面積よシも大とされてなることを特
徴とする半導体装置。an insulator base having a generally rectangular O semiconductor element accommodating opening for accommodating a semiconductor element; a generally rectangular metal plate disposed at the bottom of the opening; a semiconductor element mounted and fixed on the metal plate; In a semiconductor device having an external connection terminal disposed around an insulating substrate, and a conductive member electrically connecting an electrode of the semiconductor element and the external connection terminal, the metal plate is connected to the insulating substrate. A semiconductor device characterized in that the area of the fixing surface is larger than the area of the fixing surface of the semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56210993A JPS58115836A (en) | 1981-12-28 | 1981-12-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56210993A JPS58115836A (en) | 1981-12-28 | 1981-12-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58115836A true JPS58115836A (en) | 1983-07-09 |
Family
ID=16598544
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56210993A Pending JPS58115836A (en) | 1981-12-28 | 1981-12-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58115836A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63186438A (en) * | 1987-01-28 | 1988-08-02 | Nec Corp | Integrated circuit device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS511427A (en) * | 1974-06-18 | 1976-01-08 | Matsushita Electric Ind Co Ltd | Azobenzenjudotaino seizohoho |
-
1981
- 1981-12-28 JP JP56210993A patent/JPS58115836A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS511427A (en) * | 1974-06-18 | 1976-01-08 | Matsushita Electric Ind Co Ltd | Azobenzenjudotaino seizohoho |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63186438A (en) * | 1987-01-28 | 1988-08-02 | Nec Corp | Integrated circuit device |
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