JPS58114650A - Frame synchronizing control system - Google Patents

Abstract

PURPOSE:To decrease useless hunting operations and to assure a reproduction of data, by presetting the internal synchronizing signal with the synchronism detecting signal when a shift of the generation timing between the internal synchronizing signal and the synchronous detecting signal is within a prescribed range. CONSTITUTION:Input digital information A is read by a data reading circuit 2 on the basis of the clock which is extracted out of the corresponding information through a clock extracting circuit 1. The information A is then fed to a data processing circuit 8. An internal synchronizing signal producing circuit 3 receives the outputs of the clock signal and the output of a data reading circuit 2 and is controlled by a synchronous timing detecting circuit 10 which receives a frame synchronizing signal B given from a frame synchronism detecting circuit 4 to produce an internal synchronizing signal. The circuit 10 compares a signal D converted from a synchronizing pulse C of the circuit 3 into a certain pulse longer than the pulse C through a certain pulse width signal producing circuit 9 with the signal B. Then the circuit 3 is preset with the signal B if the signal B is within the period of the signal D. When the signal B gets out of the period of the signal D, a synchronous hunting control circuit 6 is started to have a known synchronizing operation.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frame synchronization control method, and more particularly to a frame synchronization control method for reading and processing digital transmission information such as POM (pulse code modulation) signals. In a POM system in which the digital signal is converted into a digital signal, transmitted or recorded on a recording medium, and then received or reproduced to obtain the original analog 5-1 information signal again, the digital signal is converted into a plurality of continuous signals. It is made up of frames. When receiving such digital information, decoding must be started in synchronization with the arrival of the first data in one frame, and for this purpose a frame synchronization method is adopted. That is, a frame synchronization signal having a predetermined bit pattern consisting of a plurality of pits is inserted at the beginning of each frame, and frame synchronization is performed using this frame synchronization signal.

FIG. 1 is a schematic block diagram of a conventional frame synchronization control system, in which digital transmission information including a clock signal and a frame synchronization signal is input to a clock extractor 1 and a data reading circuit 2. The clock extractor 1 is, for example, a PLL (
Based on this extracted or locked signal, the data reading circuit 2 removes signal distortion in the transmission system and recording/reproducing system and reads the digital signal before transmission or during recording. The waveform is shaped into a pulse train waveform with noise, jitter components, etc. removed.

An internal synchronization signal generator 3 is provided, which is configured to count the clock signals extracted by the clock extractor 1 and generate one internal synchronization signal for each frame. In addition, the frame synchronization signal pattern in the output data of the data reading circuit 2, for example, a pattern in which two consecutive inversions occur every 11 clocks, is detected by the timing of the clock signal, and synchronization is detected according to the generation timing of the frame synchronization signal. A frame synchronization detector 4 is provided for generating a signal. The generation timing of this frame synchronization detection signal and the internal synchronization signal is determined by a timing comparator 5.
If a timing shift is detected, the synchronization hunting controller 6 operates to perform frame synchronization hunting. This hunting is performed by controlling the clock counting contents of the internal synchronizing signal generator 3 to a preset state by the output of the controller 6. Therefore,
If the generation timing of the internal synchronization signal is shifted due to a phase shift of the clock signal, etc., this is forcibly preset at the generation timing of the frame synchronization signal to ensure frame synchronization.

The timing generator 7 operates according to this internal synchronization signal,
Data is accurately decoded by controlling the timing of the data processing circuit 8 to correspond to the frame synchronization signal.

In such a frame synchronization method, if the generation timing of the internal synchronization signal and the frame synchronization detection signal deviate, regardless of the degree of the difference, hunting operation is immediately started, and a preset is performed at the frame synchronous detection timing of the next frame. Become.

Therefore, even if the frame synchronization detection signal is located very close to the internal synchronization signal (with a deviation of 1 to 2 clocks), a hunting operation will occur and no data will be obtained until the next frame. Furthermore, if a certain portion of the data becomes equal to the frame synchronization pattern due to dropout or the like, resulting in a so-called erroneous sync, the frame synchronization detector 4 detects this and enters a hunting operation, which is undesirable.

Furthermore, even if a frame synchronization pattern cannot be detected due to dropouts or noise, the system enters a hunting operation each time, and if a frame synchronization pattern cannot be detected many times in a row, it becomes constantly in a hunting state, making it difficult to reproduce data. Become.

Therefore, an object of the present invention is to provide a frame synchronization method that can reduce unnecessary hunting operations as much as possible and ensure data reproduction.

The frame synchronization method according to the present invention is based on the clock signal.
It is equipped with means for generating an internal synchronization signal for information processing for each frame, and means for detecting the frame synchronization signal and generating a synchronization detection signal according to the detection timing. The present invention is characterized in that the generation timing of the internal synchronization signal is preset by the generation timing of the synchronization detection signal when the generation timing deviation is within a predetermined range.

The present invention will be explained below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, and parts equivalent to those in FIG. 1 are designated by the same reference numerals.

To describe only the differences from FIG. 1, the internal synchronization signal (C) for each frame from the internal synchronization signal generator 3 is input to the constant pulse width signal generator 9.

This signal generator 9 has two cascaded configurations, for example.
(monostable multivibrator), the previous stage MMV is triggered by the timing of generation of an internal synchronization signal (0) to generate a pulse with a constant width slightly shorter than one frame period. Next, the next stage MMV is triggered at the end of this pulse to generate, for example, an 8-bit width pulse, and this is used as a constant pulse width signal (DJ).This constant pulse width signal (D) Output of frame synchronization detector 4 (
A synchronization timing detector 10 is provided which receives the frame synchronization detection signal (B) as an input, and this detector 10 detects whether the generation timing of the frame synchronization detection signal (B) is within the generation period of the constant pulse width signal (■). However, if it is within this period, the internal synchronization signal generator 3 is preset by the frame synchronization detection timing to synchronize the internal synchronization signal (0) with the frame synchronization timing.

This synchronization timing detector 10 has a constant pulse width (DJ
This pulse (F) generates one pulse (F) when there is no frame synchronization detection signal (B) within the frame synchronization detection signal (F).
The synchronous hunting controller 6 counts the numbers, and only when a predetermined number is reached multiple times in succession, does the noting operation begin.
It operates to preset the internal synchronization signal generator 3 at the timing of the frame synchronization detection signal (B). The other configurations are the same as those in FIG. 1.

The operation of the circuit shown in FIG. 2 will be explained using the waveforms shown in FIGS. 3 to 6. Each part of the circuit shown in FIG. .about.(D) respectively, and each of the figures (E) shows the . . . bearing state.

FIG. 3 shows each waveform in an initial state such as when the power is turned on or when data is input, and initially the device is in the /% counting state as shown in (E). During this time, a clock is being extracted from the clock extractor 1, but it is not yet accurately synchronized with the frame synchronization signal, so the internal synchronization signal obtained by counting this clock is as shown in Figure (0). Then, at the time when the frame synchronization signal is detected, the frame synchronization detection signal b1 is generated as shown in Figure (B), and the internal synchronization signal generator 3 is preset by this generation timing regardless of the constant pulse width signal CD). frame synchronization is performed and accurate data processing is performed.

FIG. 4 shows the state of protection operation against the phase shift of the extracted clock. As mentioned above, the internal synchronization signal generator 3 counts the extracted clocks and generates an internal synchronization signal (
0), but if the extracted clock does not match the predetermined number within one frame period due to a phase shift, etc., the internal synchronization signal C1 in Figure (0) will be generated and the frame will be It becomes out of synchronization with the synchronization detection signal (B). Here, conventionally, the hunting state is immediately entered, but in this example, the internal synchronization signal C and the frame synchronization detection signal B2 are set within the range of the DJ.
Since the difference in the timing of occurrence has subsided,
The synchronization timing detector 10 detects this and presets the internal synchronization signal generator 3 according to the generation timing of the frame synchronization detection signal b2, thereby making frame synchronization possible instantly.

In this way, even if there is a clock shift of several clocks (usually 1 to 2 clocks) between one frame, a constant norm width signal (D
) is set to a width greater than that (e.g., 8 clock width), it is convenient because the transition to the 71 counting state is less likely to occur. As a lower limit, the width of this reference signal (D) must be wider than the width of the number of clock shifts between one frame (for example, if there are 588 bits between one frame, it is 1 to 2 clocks). Also, the upper limit is from the timing of the internal synchronization signal (C) to before the first operation in which the data processing circuit 8 starts data processing by the timing generator 7 (for example, from the timing of the frame synchronization signal to 17
If the data is to be latched and written to the RAM after the pit, it is necessary to set the width to be narrower than 17 clocks, and as described above, for example, 8 bits is appropriate.

Also, if there is an incorrect sink S′ in data (5),
Unless this is within the pulse width of the constant pulse width signal (D), no hunting operation will occur.

FIG. 5 shows waveforms showing a protection operation state when frame synchronization parts are successively lost due to dropout or the like. For example, when frame synchronization S is lost eight times in a row as shown in FIG. Then, due to the eighth omission, the synchronization timing detector 10 generates eight consecutive pulses (F), so the controller 6 counts these pulses and shifts to the nulling state. The internal synchronization signal generator 3 is preset by the generation timing of the next frame synchronization detection signal b3 regardless of the constant pulse width signal (D), thereby ensuring frame synchronization.

FIG. 6 shows operation waveforms when there is an erroneous sync during the hafting operation. If there is an erroneous sync S' during the non-setting period, the internal synchronization signal generator 3 is preset in synchronization with this erroneous sync S', and thereafter it processes data at the wrong timing due to this erroneous sync. During this time, since there is no frame synchronization detection signal (B) within the pulse width of the constant pulse width signal (D) and the state continues to be distorted, the synchronization timing detector 10 continuously outputs eight pulses (F). . At this point, the internal synchronization signal generator 3 is preset by the timing of the next frame synchronization detection signal b4, regardless of the constant pulse width signal CD, and frame synchronization becomes possible from then on. .

As described above, according to the present invention, the probability of shifting to a hunting operation due to clock deviation can be significantly reduced, and thus the error rate in the data processing process can be reduced. Furthermore, even if there is an erroneous sync in the data, if this sync is significantly different from the internal synchronization signal, no malfunction will occur due to this erroneous sync. Furthermore, even if the frame synchronization signal is lost, there is no immediate transition to the hunting state, which has the advantage of reducing unnecessary hunting.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a conventional frame synchronization system, FIG. 2 is a block diagram of an embodiment of the present invention, and FIGS. 3 to 6 are operational waveform diagrams in each state of the circuit of FIG. 2. Description of symbols of main parts 1...Clock extractor 3...Internal synchronization signal generator 4...Frame synchronization detector 9...Constant pulse width signal generator 10...Synchronization timing detector Applicant Pioneer Co., Ltd. Agent Patent Attorney Hajime Fujimura Onden 1st Ward Maku 2 Zu Kai 3 (D) --' (E) i-ro 4'/7"
. L4 diagram (E)

Claims (1)

[Claims] A frame synchronization control method for reading and processing digital transmission information including a clock signal and a frame synchronization signal, the method comprising means for generating an internal synchronization signal for information processing from the clock signal for each frame, and the frame synchronization signal. and generating a synchronization detection signal according to the detection timing, the generation timing of the internal synchronization signal being determined when the generation timing difference between the internal synchronization signal and the synchronization detection signal is within a predetermined range. is preset according to the generation timing of the synchronization detection signal.