JPS58114628A - Output circuit - Google Patents
Output circuitInfo
- Publication number
- JPS58114628A JPS58114628A JP56210321A JP21032181A JPS58114628A JP S58114628 A JPS58114628 A JP S58114628A JP 56210321 A JP56210321 A JP 56210321A JP 21032181 A JP21032181 A JP 21032181A JP S58114628 A JPS58114628 A JP S58114628A
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- transistor
- inverters
- output circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体集積回路に関し、特に高インピーダン
ス出力状態を有するトライステート出力回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor integrated circuits, and more particularly to tristate output circuits having high impedance output states.
ＭＯ８ＩＣの一例を示すと、従来仁の種の出力回路は、
第１図の様に、出力データ信号り、Ｄと出力フローティ
ング信号Ｈ２とにより、出力Ｊ／／。As an example of MO8IC, the conventional Jinotane output circuit is
As shown in FIG. 1, the output J// is generated by the output data signal D and the output floating signal H2.
１０“及び高インピーダンスの７０−ティングの３状態
を作っている。Three states are created: 10" and high impedance 70-ting.
そこで、例えば第２図の様に、２つのＩＣＩＣ１、ＩＣ
２の出力端子を共通信号線に結線した回路で、ｘｃｌ
ｔ ＩＣ２の各出力をフローティングにする信号Ｈ７Ｉ
、Ｈ２２が、第３図に示すタイξングで印加された場
合、ＴＷの期間間ＩＣの出力が引合うと・とＫなる。Therefore, for example, as shown in Figure 2, two ICIC1 and IC
This is a circuit in which the output terminals of 2 are connected to a common signal line,
t Signal H7I that makes each output of IC2 floating
, H22 are applied with the timing ξ shown in FIG. 3, when the outputs of the IC are attracted during the period TW, .
仁の際出力トランジスタ部ＴＩに規格以上の大きな電流
が流れる。例えばＭＯ８ＩＣの場合、動作規格２〜３ｍ
Ａに対して２０〜３０ｍＡ程度となる。In this case, a large current exceeding the standard flows through the output transistor section TI. For example, in the case of MO8IC, the operating standard is 2 to 3 m.
It is about 20 to 30 mA with respect to A.
これにより、ＩＣの誤動作のみでなく、電流経路の金属
配線、ボンディングワイヤ等の溶断等の破壊が起る。This causes not only malfunction of the IC, but also destruction of the metal wiring of the current path, bonding wires, etc., such as melting.
本発明の目的は、出力の引合いを検出して、出力トラン
ジスタをハイインピーダンスにすることにより、上記破
壊を防ぐ出力回路を提供することにある。An object of the present invention is to provide an output circuit that prevents the above-mentioned destruction by detecting an output inquiry and setting the output transistor to high impedance.
本発明の構成は、第４図に示す様に、出力トランジスタ
部ＴＩと、出力引合い検出回路ＩＤと、ＩＤの出力、デ
ータ信号り、Ｄ、出力フローティング信号Ｈｚとを入力
とする出力トランジスタ制御回路Ｓ２とから成る。As shown in FIG. 4, the configuration of the present invention includes an output transistor section TI, an output inquiry detection circuit ID, an output transistor control circuit which receives the output of the ID, a data signal D, and an output floating signal Hz. It consists of S2.
本発明の作用は、ＩＣのオン状態の出力トランジスタに
大電流が、流れたことを検出して、出力トランジスタの
入力にＩＩ遺し出力トランジスタをオフさせ電流を遮断
することである。The function of the present invention is to detect that a large current has flowed through an output transistor in an on-state of an IC, and to cut off the current by passing a large current to the input of the output transistor and turning off the output transistor.
次に本発明の実施例について図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.
第５図を参照すると、本発明の実施例は、出力トフンジ
Ｘ−齢″１゛１と、Ｔｔａ出力０舎人力と°電るインバ
ータＩ、、Ｉ３とｓ ＩＩの出力を入力とするインバー
−、ｚ Ｉ ４と、出カフ０−ティング信号Ｈ２及び出
力データ信号り、ｎを入力とする２人力ＮＯＲＩ、、Ｉ
、とｓ Ｉ？＊ ｘ、の出力をそれぞれ入力とするイ
ンバータＩ、、Ｉ−と、エフ。Referring to FIG. 5, the embodiment of the present invention is an inverter whose inputs are the outputs of inverters I, I3 and sII, which have an output power of 0 and a Tta output of 0. , z I 4, the output cuffing signal H2 and the output data signal ri, the two-man power NORI, , I
, and s I? * Inverters I, , I-, and F, each receiving the output of x.
■−の出力とＧＮＤ関にそれぞれ接続された容量Ｃｌ
＊ Ｃ２と、Ｉ！の出力を８入力、Ｉ６の出力をＲ入力
とするＲ８フリ、プ７０．プ１１とｓ Ｉ４の出力を
８入力、Ｉ・の出力をＲ入力とするＲ８フリップフロッ
プＩＩとｓＩｌ＊ Ｔｌの出力及びＲ２，Ｄ、Ｄの信
号を入力とする出力制御部Ｓ２とを含み、８２の出力を
出力トランジスタＴｌに入力して成る。■ Capacitor Cl connected to the − output and GND
* C2 and I! The output of R8 is 8 inputs, and the output of I6 is R input. It includes an R8 flip-flop II which has 8 inputs of the outputs of 11 and sI4, and an R input of the output of I, and an output control section S2 which has inputs of the output of sIl*Tl and the signals of R2, D, and D, The output of 82 is input to the output transistor Tl.
ここで、単一５ｖ電源ＭＯ８ＩＣの場合について説明す
る。出力０の正常動作レベルは、データ１０′が電流２
〜３ｍＡで０．４５Ｖ最大、データ１１′が電流０．４
〜０．６ｍＡで２．４ｖ最小程度であるので、インバー
タ１．、Ｘ、の回路しきい値電圧をそれぞれ２Ｖ、０．
８Ｖ程度に設定すると、出力電流１０ ｍＡ ？！Ｎｌ
でＩ、、Ｉ、が返転する。Here, the case of a single 5v power supply MO8IC will be explained. The normal operating level for output 0 is when data 10' is current 2.
~0.45V maximum at 3mA, data 11' is current 0.4
~0.6mA and 2.4V minimum, so inverter 1. , X, the circuit threshold voltages are set to 2V and 0.
When set to about 8V, the output current is 10 mA? ! Nl
,I,,I,returns.
１１ｖ 工１がそれぞれＶ″１“０＃に反転した時フ
リップフロップＩｌｔ”ｌｌがセットされて出力制御回
路８２に入力され、出力トランジスタをオフさせ電流を
遮断する。尚フリ、プ７０ツブＩＩ。When 11V and 1 are respectively inverted to V''1 and 0#, the flip-flop Ilt''ll is set and input to the output control circuit 82, turning off the output transistor and cutting off the current.
Ｉ、ＯＲ入力は、出力データ信号り、Ｄ及び出力フロー
ティング信号Ｈ７により作り、又、■？。The I and OR inputs are made by the output data signal, D, and the output floating signal H7, and ■? .
■＄の出力に容量を接続して適当な遅れを持たせる事に
より、正常出力時及びデータ遷移時の論動作を防ぐ。■By connecting a capacitor to the $ output to provide an appropriate delay, prevent logic operation during normal output and data transition.
本実施例によれば、ｌ”Ｄ＝翫ゝ、ＩＩ 、Ｈ２＝”Ｏ
”）である出力ゝ０”（Ｔｒｉがオフ 、 Ｔｒ ２が
オン）の状態では、出力電流が１０ｍＡ程度になると、
出力０の電位が０．８Ｖ以上になり、工＄の出力が０“
に反転してＩ、をセットしＴｒ２をオフさせる。この動
作により、規格外の大電流を遮断して破壊を防ぐ。According to this embodiment, l”D=翫ゝ, II, H2=”O
), when the output is 0 (Tri is off and Tr2 is on), when the output current becomes about 10mA,
The potential of output 0 becomes 0.8V or more, and the output of
, and sets I to turn off Tr2. This action interrupts large currents that exceed the specifications and prevents damage.
本発明は、以上説明したように、出力部に引合い検出回
路を設け、その出力を出力制御回路へ帰還して大電流を
遮断し破ＩＩｋｌ−防ぐ効果がある。As explained above, the present invention has the effect of providing an inquiry detection circuit in the output section and feeding back the output to the output control circuit to cut off a large current and prevent failure.
第１図は従来出力回路をブロック図で示した回路図。第
２図は従来の出力回路で問題となるＩＣの結線図。ＪＲ
３図は問題となる入出力信号のタイミング図。第４図は
本発明のブロック図。第５図は本発明の一実施例を示す
回路図。
Ｄ、Ｄ・・・・・・出力データの正、逆相信号、０．０
１゜０２・・・・・・出力端子、Ｔｌ・・・・・・出力
トランジスタ部、８ ｌ、 Ｓ ２ ・・・・・−出力
側ａ回Ｍ、Ｈｚ 、Ｈｚｌ、Ｒ２２・・・・・・出力フ
ローティング信号％ＩＣ１，ＩＣ２・・・・・・ トラ
イステート出力回路を有する半導体集積回路、ＴＷ・・
・・・・出力０１．０２の引合い期間、ＩＤ・・・・・
・出力引合検出回路％ １．〜Ｉ４Ｉ■６〜Ｉ。
・・・・・・出力引合い検出回路内インノ（−夕及びＮ
ＯＲ。
１１〜１．・・・・・・出力引合検出回路内のＲＳ ７
１ｊツブフロ、プ、Ｎ０ＲＩ 、Ｎ０Ｒ２・・・・・・
出力制御用ＮＯＲ回路、Ｔｒｉ 、Ｔｒ２・・・・・・
出力用トランジスタ。
Ｓｔ Ｔｔ
第１閉
第 ２１！ｌ
第３閉
第４１！］FIG. 1 is a circuit diagram showing a conventional output circuit in block diagram form. Figure 2 is a wiring diagram of an IC, which is a problem in conventional output circuits. JR
Figure 3 is a timing diagram of the problematic input/output signals. FIG. 4 is a block diagram of the present invention. FIG. 5 is a circuit diagram showing an embodiment of the present invention. D, D... Positive and negative phase signals of output data, 0.0
1゜02...Output terminal, Tl...Output transistor section, 8 l, S2...-Output side a times M, Hz, Hzl, R22...・Output floating signal %IC1, IC2... Semiconductor integrated circuit with tri-state output circuit, TW...
...Output 01.02 inquiry period, ID...
・Output inquiry detection circuit% 1. ~I4I■6~I.・・・・・・Inno in the output inquiry detection circuit (-Y and N
OR. 11-1. ...RS7 in the output inquiry detection circuit
1j Tsubufuro, Pu, N0RI, N0R2...
NOR circuit for output control, Tri, Tr2...
Output transistor. St Tt 1st close 21st! l 3rd closed 41st! ]
Claims (1)
上記検出手段の出力に基づいて上記出力トランジスタを
溶断せしめる手段とを有する出力回路。A means of detecting abnormal current flowing through the output transistor.
and means for blowing out the output transistor based on the output of the detection means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56210321A JPS58114628A (en) | 1981-12-28 | 1981-12-28 | Output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56210321A JPS58114628A (en) | 1981-12-28 | 1981-12-28 | Output circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58114628A true JPS58114628A (en) | 1983-07-08 |
Family
ID=16587484
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56210321A Pending JPS58114628A (en) | 1981-12-28 | 1981-12-28 | Output circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58114628A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4939276A (en) * | 1987-11-19 | 1990-07-03 | Hoffmann-La Roche Inc. | Concentration of natural ingredients from natural materials |
-
1981
- 1981-12-28 JP JP56210321A patent/JPS58114628A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4939276A (en) * | 1987-11-19 | 1990-07-03 | Hoffmann-La Roche Inc. | Concentration of natural ingredients from natural materials |
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